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| author | David Woodhouse <David.Woodhouse@intel.com> | 2008-10-13 17:13:56 +0100 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-10-13 17:13:56 +0100 |
| commit | e758936e02700ff88a0b08b722a3847b95283ef2 (patch) | |
| tree | 50c919bef1b459a778b85159d5929de95b6c4a01 /arch/arm/mach-lh7a40x/Kconfig | |
| parent | 239cfbde1f5843c4a24199f117d5f67f637d72d5 (diff) | |
| parent | 4480f15b3306f43bbb0310d461142b4e897ca45b (diff) | |
| download | op-kernel-dev-e758936e02700ff88a0b08b722a3847b95283ef2.zip op-kernel-dev-e758936e02700ff88a0b08b722a3847b95283ef2.tar.gz | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
include/asm-x86/statfs.h
Diffstat (limited to 'arch/arm/mach-lh7a40x/Kconfig')
| -rw-r--r-- | arch/arm/mach-lh7a40x/Kconfig | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig index 6f4c6a1..9be7466 100644 --- a/arch/arm/mach-lh7a40x/Kconfig +++ b/arch/arm/mach-lh7a40x/Kconfig @@ -40,23 +40,22 @@ config LPD7A40X_CPLD_SSP bool config LH7A40X_CONTIGMEM - bool "Disable NUMA Support" - depends on ARCH_LH7A40X + bool "Disable NUMA/SparseMEM Support" help Say Y here if your bootloader sets the SROMLL bit(s) in the SDRAM controller, organizing memory as a contiguous - array. This option will disable CONFIG_DISCONTIGMEM and - force the kernel to manage all memory in one node. + array. This option will disable sparse memory support + and force the kernel to manage all memory in one node. - Setting this option incorrectly may prevent the kernel from - booting. It is OK to leave it N. + Setting this option incorrectly may prevent the kernel + from booting. It is OK to leave it N. For more information, consult <file:Documentation/arm/Sharp-LH/SDRAM>. config LH7A40X_ONE_BANK_PER_NODE bool "Optimize NUMA Node Tables for Size" - depends on ARCH_LH7A40X && !LH7A40X_CONTIGMEM + depends on !LH7A40X_CONTIGMEM help Say Y here to produce compact memory node tables. By default pairs of adjacent physical RAM banks are managed |
