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author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-01-20 18:03:56 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-01-20 18:03:56 -0800 |
commit | 6b5a12dbca7a8681ecb78dbebaedc1f8364ebd10 (patch) | |
tree | 497bc67a98e8bf5247dd453d05ab0dba4c31e424 /arch/arm/mach-ks8695/regs-mem.h | |
parent | 5083c54264d21bf9b8a4766068f51581854d772c (diff) | |
parent | 2cb58c016673c4c8b8ec59e71c5ec4b2c6a76afb (diff) | |
download | op-kernel-dev-6b5a12dbca7a8681ecb78dbebaedc1f8364ebd10.zip op-kernel-dev-6b5a12dbca7a8681ecb78dbebaedc1f8364ebd10.tar.gz |
Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform code updates from Arnd Bergmann:
"This branch is the culmination of 5 years of effort to bring the ARMv6
and ARMv7 platforms together such that they can all be enabled and
boot the same kernel. It has been a tremendous amount of cleanup and
refactoring by a huge number of people, and creation of several new
(and major) subsystems to better abstract out all the platform details
in an appropriate manner.
The bulk of this branch is a large patchset from Arnd that brings
several of the more minor and older platforms we have closer to
multiplatform support. Among these are MMP, S3C64xx, Orion5x, mv78xx0
and realview Much of this is moving around header files from old mach
directories, but there are also some cleanup patches of debug_ll
(lowlevel debug per-platform options) and other parts.
Linus Walleij also has some patchs to clean up the older ARM Realview
platforms by finally introducing DT support, and Rob Herring has some
for ARM Versatile which is now DT-only. Both of these platforms are
now multiplatform.
Finally, a couple of patches from Russell for Dove PMU, and a fix from
Valentin Rothberg for Exynos ADC, which were rebased on top of the
series to avoid conflicts"
* tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits)
ARM: realview: don't select SMP_ON_UP for UP builds
ARM: s3c: simplify s3c_irqwake_{e,}intallow definition
ARM: s3c64xx: fix pm-debug compilation
iio: exynos-adc: fix irqf_oneshot.cocci warnings
ARM: realview: build realview-dt SMP support only when used
ARM: realview: select apropriate targets
ARM: realview: clean up header files
ARM: realview: make all header files local
ARM: no longer make CPU targets visible separately
ARM: integrator: use explicit core module options
ARM: realview: enable multiplatform
ARM: make default platform work for NOMMU
ARM: debug-ll: move DEBUG_LL_UART_EFM32 to correct Kconfig location
ARM: defconfig: use correct debug_ll settings
ARM: versatile: convert to multi-platform
ARM: versatile: merge mach code into a single file
ARM: versatile: switch to DT only booting and remove legacy code
ARM: versatile: add DT based PCI detection
ARM: pxa: mark ezx structures as __maybe_unused
ARM: pxa: mark raumfeld init functions as __maybe_unused
...
Diffstat (limited to 'arch/arm/mach-ks8695/regs-mem.h')
-rw-r--r-- | arch/arm/mach-ks8695/regs-mem.h | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/arm/mach-ks8695/regs-mem.h b/arch/arm/mach-ks8695/regs-mem.h new file mode 100644 index 0000000..55806bc --- /dev/null +++ b/arch/arm/mach-ks8695/regs-mem.h @@ -0,0 +1,89 @@ +/* + * arch/arm/mach-ks8695/include/mach/regs-mem.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Memory Controller registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_MEM_H +#define KS8695_MEM_H + +#define KS8695_MEM_OFFSET (0xF0000 + 0x4000) +#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) +#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) + + +/* + * Memory Controller Registers + */ +#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ +#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ +#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ +#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ +#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ +#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ +#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ +#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ +#define KS8695_SDGCON (0x38) /* SDRAM General Control */ +#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ +#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ + + +/* External I/O Access Control Registers */ +#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ +#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ +#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ +#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ +#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ +#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ + +/* ROM/SRAM/Flash Control Register */ +#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ +#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ +#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ +#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ +#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ +#define PMC_NORMAL (0 << 0) +#define PMC_4WORD (1 << 0) +#define PMC_8WORD (2 << 0) +#define PMC_16WORD (3 << 0) + +/* External I/O and ROM/SRAM/Flash General Register */ +#define ERGCON_TMULT (3 << 28) /* Time Multiplier */ +#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ +#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ +#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ +#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ +#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ + +/* SDRAM Control Register */ +#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ +#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ +#define SDCON_DBCAB (3 << 8) /* Column Address Bits */ +#define SDCON_DBBNUM (1 << 3) /* Number of Banks */ +#define SDCON_DBDBW (3 << 1) /* Data Bus Width */ + +/* SDRAM General Control Register */ +#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ +#define SDGCON_SDCAS (3 << 0) /* CAS latency */ + +/* SDRAM Buffer Control Register */ +#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ +#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ +#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ +#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ +#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ +#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ +#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ +#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ + +/* SDRAM Refresh Timer Register */ +#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ + + +#endif |