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| author | Linus Walleij <linus.walleij@linaro.org> | 2012-08-29 20:26:42 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2012-09-05 08:48:56 +0200 |
| commit | 70adc3f32adc2fb90b0107c020678588e4cf9f51 (patch) | |
| tree | 69ca380e6e0cdf7a6d8aa45bcb3e332a2b7b3581 /arch/arm/mach-ks8695/include | |
| parent | fea7a08acb13524b47711625eebea40a0ede69a0 (diff) | |
| download | op-kernel-dev-70adc3f32adc2fb90b0107c020678588e4cf9f51.zip op-kernel-dev-70adc3f32adc2fb90b0107c020678588e4cf9f51.tar.gz | |
ARM: ks8695: merge the timer header into the timer driver
This <mach/regs-timer.h> is broadcasted in the entire kernel for
no good reason, since it's only used by the timer driver. Merge
it into the driver.
Tested-by: Greg Ungerer <gerg@snapgear.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ks8695/include')
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-timer.h | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h deleted file mode 100644 index e620cda..0000000 --- a/arch/arm/mach-ks8695/include/mach/regs-timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-timer.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Timer registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_TIMER_H -#define KS8695_TIMER_H - -#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) -#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) -#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) - - -/* - * Timer registers - */ -#define KS8695_TMCON (0x00) /* Timer Control Register */ -#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ -#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ -#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ -#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ - - -/* Timer Control Register */ -#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ -#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ - -/* Timer0 Timeout Counter Register */ -#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ - - -#endif |
