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authorLennert Buytenhek <buytenh@wantstofly.org>2005-11-06 14:34:13 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-06 14:34:13 +0000
commit7240f1f183f085f6b7af44ec274b5b6123dfdead (patch)
treea68b0548c7c9adc78cdd3881029fdef1d8d53252 /arch/arm/mach-ixp2000
parent84613387cb60bc760a4588822cd61fb88e1d7fad (diff)
downloadop-kernel-dev-7240f1f183f085f6b7af44ec274b5b6123dfdead.zip
op-kernel-dev-7240f1f183f085f6b7af44ec274b5b6123dfdead.tar.gz
[ARM] 3114/1: use ixp2000_reg_wrb in ixp2000 uengine loader
Patch from Lennert Buytenhek Make the uengine loader use ixp2000_reg_wrb in the right places. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ixp2000')
-rw-r--r--arch/arm/mach-ixp2000/uengine.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mach-ixp2000/uengine.c b/arch/arm/mach-ixp2000/uengine.c
index 43e2343..ec4e007 100644
--- a/arch/arm/mach-ixp2000/uengine.c
+++ b/arch/arm/mach-ixp2000/uengine.c
@@ -91,8 +91,8 @@ EXPORT_SYMBOL(ixp2000_uengine_csr_write);
void ixp2000_uengine_reset(u32 uengine_mask)
{
- ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
- ixp2000_reg_write(IXP2000_RESET1, 0);
+ ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
+ ixp2000_reg_wrb(IXP2000_RESET1, 0);
}
EXPORT_SYMBOL(ixp2000_uengine_reset);
@@ -452,21 +452,20 @@ static int __init ixp2000_uengine_init(void)
/*
* Reset microengines.
*/
- ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask);
- ixp2000_reg_write(IXP2000_RESET1, 0);
+ ixp2000_uengine_reset(ixp2000_uengine_mask);
/*
* Synchronise timestamp counters across all microengines.
*/
value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
- ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80);
+ ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
for (uengine = 0; uengine < 32; uengine++) {
if (ixp2000_uengine_mask & (1 << uengine)) {
ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
}
}
- ixp2000_reg_write(IXP2000_MISC_CONTROL, value | 0x80);
+ ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80);
return 0;
}
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