Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc

* 'next/soc' of git://git.linaro.org/people/arnd/arm-soc: (21 commits)
  MAINTAINERS: add ARM/FREESCALE IMX6 entry
  arm/imx: merge i.MX3 and i.MX6
  arm/imx6q: add suspend/resume support
  arm/imx6q: add device tree machine support
  arm/imx6q: add smp and cpu hotplug support
  arm/imx6q: add core drivers clock, gpc, mmdc and src
  arm/imx: add gic_handle_irq function
  arm/imx6q: add core definitions and low-level debug uart
  arm/imx6q: add device tree source
  ARM: highbank: add suspend support
  ARM: highbank: Add cpu hotplug support
  ARM: highbank: add SMP support
  MAINTAINERS: add Calxeda Highbank ARM platform
  ARM: add Highbank core platform support
  ARM: highbank: add devicetree source
  ARM: l2x0: add empty l2x0_of_init
  picoxcell: add a definition of VMALLOC_END
  picoxcell: remove custom ioremap implementation
  picoxcell: add the DTS for the PC7302 board
  picoxcell: add the DTS for pc3x2 and pc3x3 devices
  ...

Fix up trivial conflicts in arch/arm/Kconfig, and some more header file
conflicts in arch/arm/mach-omap2/board-generic.c (as per an ealier merge
by Arnd).

1 files changed, 70 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
new file mode 100644
index 0000000..f20f191
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+extern unsigned long phys_l2x0_saved_regs;
+
+static int imx6q_suspend_finish(unsigned long val)
+{
+	cpu_do_idle();
+	return 0;
+}
+
+static int imx6q_pm_enter(suspend_state_t state)
+{
+	switch (state) {
+	case PM_SUSPEND_MEM:
+		imx6q_set_lpm(STOP_POWER_OFF);
+		imx_gpc_pre_suspend();
+		imx_set_cpu_jump(0, v7_cpu_resume);
+		/* Zzz ... */
+		cpu_suspend(0, imx6q_suspend_finish);
+		imx_smp_prepare();
+		imx_gpc_post_resume();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct platform_suspend_ops imx6q_pm_ops = {
+	.enter = imx6q_pm_enter,
+	.valid = suspend_valid_only_mem,
+};
+
+void __init imx6q_pm_init(void)
+{
+	/*
+	 * The l2x0 core code provides an infrastucture to save and restore
+	 * l2x0 registers across suspend/resume cycle.  But because imx6q
+	 * retains L2 content during suspend and needs to resume L2 before
+	 * MMU is enabled, it can only utilize register saving support and
+	 * have to take care of restoring on its own.  So we save physical
+	 * address of the data structure used by l2x0 core to save registers,
+	 * and later restore the necessary ones in imx6q resume entry.
+	 */
+	phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
+
+	suspend_set_ops(&imx6q_pm_ops);
+}