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| author | Anson Huang <b20788@freescale.com> | 2014-06-23 16:42:43 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-07-18 16:11:30 +0800 |
| commit | dfea953ae221111c14d2fcfebad7b1973a0f49bd (patch) | |
| tree | 08b6f64b00c0b058a8c05017c8a6c233d8985131 /arch/arm/mach-imx/pm-imx6.c | |
| parent | d2d2e54d6655d78e619bfa22e186d82ca5d6e880 (diff) | |
| download | op-kernel-dev-dfea953ae221111c14d2fcfebad7b1973a0f49bd.zip op-kernel-dev-dfea953ae221111c14d2fcfebad7b1973a0f49bd.tar.gz | |
ARM: imx: mem bit must be cleared before entering DSM mode
According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/pm-imx6.c')
| -rw-r--r-- | arch/arm/mach-imx/pm-imx6.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 331055b..b3c770d 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -199,11 +199,13 @@ struct imx6_cpu_pm_info { u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ } __aligned(8); -void imx6q_set_int_mem_clk_lpm(void) +void imx6q_set_int_mem_clk_lpm(bool enable) { u32 val = readl_relaxed(ccm_base + CGPR); - val |= BM_CGPR_INT_MEM_CLK_LPM; + val &= ~BM_CGPR_INT_MEM_CLK_LPM; + if (enable) + val |= BM_CGPR_INT_MEM_CLK_LPM; writel_relaxed(val, ccm_base + CGPR); } @@ -334,6 +336,7 @@ static int imx6q_pm_enter(suspend_state_t state) switch (state) { case PM_SUSPEND_MEM: imx6q_set_lpm(STOP_POWER_OFF); + imx6q_set_int_mem_clk_lpm(false); imx6q_enable_wb(true); /* * For suspend into ocram, asm code already take care of @@ -352,6 +355,7 @@ static int imx6q_pm_enter(suspend_state_t state) imx_gpc_post_resume(); imx6q_enable_rbc(false); imx6q_enable_wb(false); + imx6q_set_int_mem_clk_lpm(true); imx6q_set_lpm(WAIT_CLOCKED); break; default: |
