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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-01 18:19:05 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-01 18:19:05 -0700
commit61464c8357c8f6b780e4c44f5c79471799c51ca7 (patch)
tree4509cf075403965528f380f2f825c46908fb7d4e /arch/arm/mach-imx/clk-pllv1.c
parent47061eda2584b9e4516d1e3a9713406a3a559ac8 (diff)
parent9cf1c871526cf6bfec2a653e1e068ee72592542c (diff)
downloadop-kernel-dev-61464c8357c8f6b780e4c44f5c79471799c51ca7.zip
op-kernel-dev-61464c8357c8f6b780e4c44f5c79471799c51ca7.tar.gz
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc general cleanups from Olof Johansson: "This is a large branch that contains a handful of different cleanups: - Fixing up the I/O space remapping on PCI on ARM. This is a series from Rob Herring that restructures how all pci devices allocate I/O space, and it's part of the work to allow multiplatform kernels. - A number of cleanup series for OMAP, moving and removing some headers, sparse irq rework and in general preparation for multiplatform. - Final removal of all non-DT boards for Tegra, it is now device-tree-only! - Removal of a stale platform, nxp4008. It's an old mobile chipset that is no longer in use, and was very likely never really used with a mainline kernel. We have not been able to find anyone interested in keeping it around in the kernel. - Removal of the legacy dmaengine driver on tegra + A handful of other things that I haven't described above." Fix up some conflicts with the staging tree (and because nxp4008 was removed) * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (184 commits) ARM: OMAP2+: serial: Change MAX_HSUART_PORTS to 6 ARM: OMAP4: twl-common: Support for additional devices on i2c1 bus ARM: mmp: using for_each_set_bit to simplify the code ARM: tegra: harmony: fix ldo7 regulator-name ARM: OMAP2+: Make omap4-keypad.h local ARM: OMAP2+: Make l4_3xxx.h local ARM: OMAP2+: Make l4_2xxx.h local ARM: OMAP2+: Make l3_3xxx.h local ARM: OMAP2+: Make l3_2xxx.h local ARM: OMAP1: Move irda.h from plat to mach ARM: OMAP2+: Make hdq1w.h local ARM: OMAP2+: Make gpmc-smsc911x.h local ARM: OMAP2+: Make gpmc-smc91x.h local ARM: OMAP1: Move flash.h from plat to mach ARM: OMAP2+: Make debug-devices.h local ARM: OMAP1: Move board-voiceblue.h from plat to mach ARM: OMAP1: Move board-sx1.h from plat to mach ARM: OMAP2+: Make omap-wakeupgen.h local ARM: OMAP2+: Make omap-secure.h local ARM: OMAP2+: Make ctrl_module_wkup_44xx.h local ...
Diffstat (limited to 'arch/arm/mach-imx/clk-pllv1.c')
-rw-r--r--arch/arm/mach-imx/clk-pllv1.c49
1 files changed, 47 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 2d856f9c..02be731 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -6,7 +6,7 @@
#include <linux/err.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/clock.h>
+
#include "clk.h"
/**
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_pllv1 *pll = to_clk_pllv1(hw);
+ long long ll;
+ int mfn_abs;
+ unsigned int mfi, mfn, mfd, pd;
+ u32 reg;
+ unsigned long rate;
+
+ reg = readl(pll->base);
+
+ /*
+ * Get the resulting clock rate from a PLL register value and the input
+ * frequency. PLLs with this register layout can be found on i.MX1,
+ * i.MX21, i.MX27 and i,MX31
+ *
+ * mfi + mfn / (mfd + 1)
+ * f = 2 * f_ref * --------------------
+ * pd + 1
+ */
+
+ mfi = (reg >> 10) & 0xf;
+ mfn = reg & 0x3ff;
+ mfd = (reg >> 16) & 0x3ff;
+ pd = (reg >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ mfn_abs = mfn;
+
+ /*
+ * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+ * 2's complements number
+ */
+ if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+ mfn_abs = 0x400 - mfn;
+
+ rate = parent_rate * 2;
+ rate /= pd + 1;
+
+ ll = (unsigned long long)rate * mfn_abs;
+
+ do_div(ll, mfd + 1);
+
+ if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+ ll = -ll;
+
+ ll = (rate * mfi) + ll;
- return mxc_decode_pll(readl(pll->base), parent_rate);
+ return ll;
}
struct clk_ops clk_pllv1_ops = {
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