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author | Arnd Bergmann <arnd@arndb.de> | 2011-10-07 21:57:31 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-07 21:57:31 +0200 |
commit | 526b264163068f77c5f2409031f5e25caf3900a9 (patch) | |
tree | 196e7581f1546e48ba392ff099f369e5c622636b /arch/arm/mach-imx/cache-l2x0.c | |
parent | 4c4cbce68f57555cddb9d77da333bf50875148ce (diff) | |
parent | 05d900c9d8ce536c6792efb323c82b1c97b54bf9 (diff) | |
download | op-kernel-dev-526b264163068f77c5f2409031f5e25caf3900a9.zip op-kernel-dev-526b264163068f77c5f2409031f5e25caf3900a9.tar.gz |
Merge branch 'imx/cleanup' into imx/devel
This helps resolve the conflicts between the imx cleanups and the
new code that has gone into the imx tree.
Conflict resolution was originally done by Sascha Hauer.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/cache-l2x0.c')
-rw-r--r-- | arch/arm/mach-imx/cache-l2x0.c | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c deleted file mode 100644 index e5538a4..0000000 --- a/arch/arm/mach-imx/cache-l2x0.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Sascha Hauer <s.hauer@pengutronix.de> - * Juergen Beisert <j.beisert@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/err.h> -#include <linux/kernel.h> - -#include <asm/hardware/cache-l2x0.h> - -#include <mach/hardware.h> - -static int mxc_init_l2x0(void) -{ - void __iomem *l2x0_base; - void __iomem *clkctl_base; - - if (!cpu_is_mx31() && !cpu_is_mx35()) - return 0; - -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value. - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (IS_ERR(l2x0_base)) { - printk(KERN_ERR "remapping L2 cache area failed with %ld\n", - PTR_ERR(l2x0_base)); - return 0; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); - - return 0; -} -early_initcall(mxc_init_l2x0); |