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authorOlof Johansson <olof@lixom.net>2012-10-01 14:33:55 -0700
committerOlof Johansson <olof@lixom.net>2012-10-01 14:33:55 -0700
commit8b1a13b02812b60b88920801363920956691feb3 (patch)
treecf140e1dfd5754aef0a59003cf9266aad003b8f5 /arch/arm/mach-exynos
parent5c008d7029fcd12a9a54fa618781b71353f6c4bd (diff)
parent04ef037c926ddb31088c976538e29eada4fd1490 (diff)
downloadop-kernel-dev-8b1a13b02812b60b88920801363920956691feb3.zip
op-kernel-dev-8b1a13b02812b60b88920801363920956691feb3.tar.gz
Merge branch 'next/drivers' into HEAD
Conflicts: arch/arm/boot/dts/omap4.dtsi arch/arm/mach-clps711x/common.c arch/arm/mach-omap1/board-h2.c arch/arm/mach-omap1/board-h3.c arch/arm/mach-omap1/leds-h2p2-debug.c arch/arm/mach-omap1/leds.c arch/arm/mach-pnx4008/time.c arch/arm/plat-omap/debug-leds.c drivers/Makefile drivers/bus/omap_l3_noc.c
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig2
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c86
-rw-r--r--arch/arm/mach-exynos/common.c26
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h5
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c8
5 files changed, 127 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6c3299e..412884d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -405,6 +405,8 @@ config MACH_EXYNOS4_DT
select USE_OF
select ARM_AMBA
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+ select PINCTRL
+ select PINCTRL_EXYNOS4
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the Exynos4 SoC based board.
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 618d0aa..f3171c3 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -547,6 +547,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
};
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+ .clk = {
+ .name = "mout_aclk_300_gscl_mid",
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
+ [0] = &exynos5_clk_sclk_vpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+ .sources = exynos5_clkset_aclk_300_mid1_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+ .clk = {
+ .name = "mout_aclk_300_gscl_mid1",
+ },
+ .sources = &exynos5_clkset_aclk_300_gscl_mid1,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+ [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+ [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+ .sources = exynos5_clkset_aclk_300_gscl_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+ .clk = {
+ .name = "mout_aclk_300_gscl",
+ },
+ .sources = &exynos5_clkset_aclk_300_gscl,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_gscl_300_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_gscl_300 = {
+ .sources = exynos5_clk_src_gscl_300_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+ .clk = {
+ .name = "aclk_300_gscl",
+ },
+ .sources = &exynos5_clk_src_gscl_300,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
static struct clk exynos5_init_clocks_off[] = {
{
.name = "timers",
@@ -755,6 +817,26 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 18),
}, {
+ .name = "gscl",
+ .devname = "exynos-gsc.0",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.1",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.2",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.3",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
@@ -1225,6 +1307,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_aclk_266,
&exynos5_clk_aclk_200,
&exynos5_clk_aclk_166,
+ &exynos5_clk_aclk_300_gscl,
+ &exynos5_clk_mout_aclk_300_gscl,
+ &exynos5_clk_mout_aclk_300_gscl_mid,
+ &exynos5_clk_mout_aclk_300_gscl_mid1,
&exynos5_clk_aclk_66_pre,
&exynos5_clk_aclk_66,
&exynos5_clk_dout_mmc0,
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..715b690 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -980,6 +980,32 @@ static int __init exynos_init_irq_eint(void)
{
int irq;
+#ifdef CONFIG_PINCTRL_SAMSUNG
+ /*
+ * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
+ * functionality along with support for external gpio and wakeup
+ * interrupts. If the samsung pinctrl driver is enabled and includes
+ * the wakeup interrupt support, then the setting up external wakeup
+ * interrupts here can be skipped. This check here is temporary to
+ * allow exynos4 platforms that do not use Samsung pinctrl driver to
+ * co-exist with platforms that do. When all of the Samsung Exynos4
+ * platforms switch over to using the pinctrl driver, the wakeup
+ * interrupt support code here can be completely removed.
+ */
+ struct device_node *pctrl_np, *wkup_np;
+ const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+ const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
+
+ for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
+ if (of_device_is_available(pctrl_np)) {
+ wkup_np = of_find_compatible_node(pctrl_np, NULL,
+ wkup_compat);
+ if (wkup_np)
+ return -ENODEV;
+ }
+ }
+#endif
+
if (soc_is_exynos5250())
exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
else
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 6d33f50..5aa77f9 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -121,6 +121,11 @@
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
+#define EXYNOS5_PA_GSC0 0x13E00000
+#define EXYNOS5_PA_GSC1 0x13E10000
+#define EXYNOS5_PA_GSC2 0x13E20000
+#define EXYNOS5_PA_GSC3 0x13E30000
+
#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..e707eb1 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -56,6 +56,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
+ "exynos-gsc.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
+ "exynos-gsc.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
+ "exynos-gsc.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
+ "exynos-gsc.3", NULL),
{},
};
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