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authorNicolas Pitre <nicolas.pitre@linaro.org>2014-06-24 18:36:32 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-07-18 11:58:04 +0100
commitfbb0499091dc1132995214a47188214602fd75c9 (patch)
treeadae97ca27e1ac6823943156dac3c96729c3872c /arch/arm/mach-exynos
parent3592d7e002438980f9ce4a399f21ec94cbf071ea (diff)
downloadop-kernel-dev-fbb0499091dc1132995214a47188214602fd75c9.zip
op-kernel-dev-fbb0499091dc1132995214a47188214602fd75c9.tar.gz
ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster using the MCPM loopback
The Chromebook firmware doesn't enable the CCI for the boot cpu, and arguably it shouldn't have to either. Let's have the kernel handle the CCI on its own for the boot CPU the same way it does it for secondary CPUs by using the MCPM loopback. This allows to boot all 8 cores on exynos5420-peach-pit, exynos5800-peach-pi and ARM Chromebook 2. Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Tushar Behera <tushar.b@samsung.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index ace0ed6..0d95bc8 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -289,6 +289,19 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
"b cci_enable_port_for_self");
}
+static void __init exynos_cache_off(void)
+{
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+ /* disable L2 prefetching on the Cortex-A15 */
+ asm volatile(
+ "mcr p15, 1, %0, c15, c0, 3\n\t"
+ "isb\n\t"
+ "dsb"
+ : : "r" (0x400));
+ }
+ exynos_v7_exit_coherency_flush(all);
+}
+
static const struct of_device_id exynos_dt_mcpm_match[] = {
{ .compatible = "samsung,exynos5420" },
{ .compatible = "samsung,exynos5800" },
@@ -332,6 +345,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(&exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
+ if (!ret)
+ ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
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