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authorChanghwan Youn <chaos.youn@samsung.com>2011-10-04 17:08:57 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 18:35:02 +0900
commit90a454b4c5ef16ec71797b3dcaf454e604c786a3 (patch)
tree11cf8fcec590c912b4cb35a24232337f1f7e1946 /arch/arm/mach-exynos4/platsmp.c
parentb88b1cc72e2bbb55c56f2df55b5ad59a18ad1464 (diff)
downloadop-kernel-dev-90a454b4c5ef16ec71797b3dcaf454e604c786a3.zip
op-kernel-dev-90a454b4c5ef16ec71797b3dcaf454e604c786a3.tar.gz
ARM: EXYNOS4: Add functions for gic interrupt handling
This patch adds two functions for gic interrupt handling. 1. Add interrupt handling of 4 cores. 2. Dynamically set gic bank offset according to the type of soc. Gic bank offset of EXYNOS4412 is 0x4000 while the offset of EXYNOS4210 and EXYNOS4212 is 0x8000. This patch is necessary because EXYNOS4 socs cannot support GIC register banking as described in commit aab74d3e75364. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/platsmp.c')
-rw-r--r--arch/arm/mach-exynos4/platsmp.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index a3346e3..d5f0f29 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -32,6 +32,7 @@
#include <plat/cpu.h>
+extern unsigned int gic_bank_offset;
extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -67,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos4_gic_secondary_init(void)
{
void __iomem *dist_base = S5P_VA_GIC_DIST +
- (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ (gic_bank_offset * smp_processor_id());
void __iomem *cpu_base = S5P_VA_GIC_CPU +
- (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ (gic_bank_offset * smp_processor_id());
int i;
/*
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