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author | Kukjin Kim <kgene.kim@samsung.com> | 2011-11-06 13:54:56 +0900 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-11-06 13:54:56 +0900 |
commit | 830145796a5c8f1ca3f87ea619063c1d99a57df5 (patch) | |
tree | e72a0ecacfcce228c46d93c946cfd65a44cc1fd3 /arch/arm/mach-exynos/setup-i2c0.c | |
parent | e700e41d9abfbf9fee01e979a41b185695132c19 (diff) | |
download | op-kernel-dev-830145796a5c8f1ca3f87ea619063c1d99a57df5.zip op-kernel-dev-830145796a5c8f1ca3f87ea619063c1d99a57df5.tar.gz |
ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
made for plaforms based on EXYNOS4 SoCs. But since upcoming
Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
codes in current mach-exynos4, one mach-exynos directory will
be used for them.
This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
avoid changing in driver side.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/setup-i2c0.c')
-rw-r--r-- | arch/arm/mach-exynos/setup-i2c0.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c new file mode 100644 index 0000000..d395bd1 --- /dev/null +++ b/arch/arm/mach-exynos/setup-i2c0.c @@ -0,0 +1,26 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c0.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include <linux/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); +} |