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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-06 12:25:11 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-06 12:25:11 -0800
commit534baf55dd16d5de9c8d045190469eef9d31ffff (patch)
treea32ca9cf98cf4a9d1f483e274c41cd8cf32b5664 /arch/arm/mach-exynos/setup-fimd0.c
parentddf8a0d385979065af7be086a4b89b6a645fe340 (diff)
parent830145796a5c8f1ca3f87ea619063c1d99a57df5 (diff)
downloadop-kernel-dev-534baf55dd16d5de9c8d045190469eef9d31ffff.zip
op-kernel-dev-534baf55dd16d5de9c8d045190469eef9d31ffff.tar.gz
Merge branch 'next/move' of git://git.linaro.org/people/arnd/arm-soc
* 'next/move' of git://git.linaro.org/people/arnd/arm-soc: ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos ARM: EXYNOS4: convert MCT to percpu interrupt API ARM: SAMSUNG: Add clk enable/disable of pwm ARM: SAMSUNG: Fix compile error due to kfree
Diffstat (limited to 'arch/arm/mach-exynos/setup-fimd0.c')
-rw-r--r--arch/arm/mach-exynos/setup-fimd0.c43
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
new file mode 100644
index 0000000..07a6dbe
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimd0.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-exynos4/setup-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Base Exynos4 FIMD 0 configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-fb-v4.h>
+
+#include <mach/map.h>
+
+void exynos4_fimd0_gpio_setup_24bpp(void)
+{
+ unsigned int reg;
+
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
+
+ /*
+ * Set DISPLAY_CONTROL register for Display path selection.
+ *
+ * DISPLAY_CONTROL[1:0]
+ * ---------------------
+ * 00 | MIE
+ * 01 | MDINE
+ * 10 | FIMD : selected
+ * 11 | FIMD
+ */
+ reg = __raw_readl(S3C_VA_SYS + 0x0210);
+ reg |= (1 << 1);
+ __raw_writel(reg, S3C_VA_SYS + 0x0210);
+}
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