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| author | Sachin Kamat <sachin.kamat@linaro.org> | 2012-06-20 16:34:25 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-07-13 06:45:55 +0900 |
| commit | c4c713554407a4afa2c1cadcc0f10e199742a4bc (patch) | |
| tree | 93959b3ff4ad5a6111300aea06fccdd2b0a5687f /arch/arm/mach-exynos/include/mach/regs-usb-phy.h | |
| parent | 7d896aaceb0ac361abf581b3b21de20f52da0ce9 (diff) | |
| download | op-kernel-dev-c4c713554407a4afa2c1cadcc0f10e199742a4bc.zip op-kernel-dev-c4c713554407a4afa2c1cadcc0f10e199742a4bc.tar.gz | |
ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
Adds clock setting entries for EXYNOS4212 and EXYNOS4412 platforms.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
[fixed compilation warning which is reported by Arnd Bergmann]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-usb-phy.h')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3..0727773 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -35,11 +35,21 @@ #define PHY1_COMMON_ON_N (1 << 7) #define PHY0_COMMON_ON_N (1 << 4) #define PHY0_ID_PULLUP (1 << 2) -#define CLKSEL_MASK (0x3 << 0) -#define CLKSEL_SHIFT (0) -#define CLKSEL_48M (0x0 << 0) -#define CLKSEL_12M (0x2 << 0) -#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_CLKSEL_SHIFT (0) + +#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) +#define EXYNOS4210_CLKSEL_48M (0x0 << 0) +#define EXYNOS4210_CLKSEL_12M (0x2 << 0) +#define EXYNOS4210_CLKSEL_24M (0x3 << 0) + +#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) +#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) +#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) +#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) +#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) +#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) |
