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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-05-23 19:28:04 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-23 19:28:04 +0100
commit9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0 (patch)
tree894bb6a3fb409c6ac5f0374f5a1f656918bc35cd /arch/arm/mach-davinci
parentec19628d72cff8f80220b7cedba089074ac6a599 (diff)
parentdc7ad3b3d5f1cd0a0d16c05dd3ad3898979d261e (diff)
downloadop-kernel-dev-9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0.zip
op-kernel-dev-9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0.tar.gz
Merge branch 'devel-stable' into for-linus
Conflicts: arch/arm/Kconfig arch/arm/mach-ns9xxx/include/mach/uncompress.h
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h5
-rw-r--r--arch/arm/mach-davinci/irq.c93
2 files changed, 23 insertions, 75 deletions
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 47723e8..78d8068 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,8 +25,7 @@
#include <mach/serial.h>
-static u32 *uart;
-static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+u32 *uart;
/* PORT_16C550A, in polled non-fifo mode */
static void putc(char c)
@@ -44,6 +43,8 @@ static inline void flush(void)
static inline void set_uart_info(u32 phys, void * __iomem virt)
{
+ u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+
uart = (u32 *)phys;
uart_info[0] = phys;
uart_info[1] = (u32)virt;
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index e6269a6..bfe68ec 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -29,8 +29,6 @@
#include <mach/common.h>
#include <asm/mach/irq.h>
-#define IRQ_BIT(irq) ((irq) & 0x1f)
-
#define FIQ_REG0_OFFSET 0x0000
#define FIQ_REG1_OFFSET 0x0004
#define IRQ_REG0_OFFSET 0x0008
@@ -42,78 +40,33 @@
#define IRQ_INTPRI0_REG_OFFSET 0x0030
#define IRQ_INTPRI7_REG_OFFSET 0x004C
-static inline unsigned int davinci_irq_readl(int offset)
-{
- return __raw_readl(davinci_intc_base + offset);
-}
-
static inline void davinci_irq_writel(unsigned long value, int offset)
{
__raw_writel(value, davinci_intc_base + offset);
}
-/* Disable interrupt */
-static void davinci_mask_irq(struct irq_data *d)
+static __init void
+davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
- unsigned int mask;
- u32 l;
-
- mask = 1 << IRQ_BIT(d->irq);
-
- if (d->irq > 31) {
- l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
- l &= ~mask;
- davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
- } else {
- l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
- l &= ~mask;
- davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
- }
-}
-
-/* Enable interrupt */
-static void davinci_unmask_irq(struct irq_data *d)
-{
- unsigned int mask;
- u32 l;
-
- mask = 1 << IRQ_BIT(d->irq);
-
- if (d->irq > 31) {
- l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
- l |= mask;
- davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
- } else {
- l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
- l |= mask;
- davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
- }
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+
+ gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+ ct = gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+
+ ct->regs.ack = IRQ_REG0_OFFSET;
+ ct->regs.mask = IRQ_ENT_REG0_OFFSET;
+ irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
-/* EOI interrupt */
-static void davinci_ack_irq(struct irq_data *d)
-{
- unsigned int mask;
-
- mask = 1 << IRQ_BIT(d->irq);
-
- if (d->irq > 31)
- davinci_irq_writel(mask, IRQ_REG1_OFFSET);
- else
- davinci_irq_writel(mask, IRQ_REG0_OFFSET);
-}
-
-static struct irq_chip davinci_irq_chip_0 = {
- .name = "AINTC",
- .irq_ack = davinci_ack_irq,
- .irq_mask = davinci_mask_irq,
- .irq_unmask = davinci_unmask_irq,
-};
-
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
- unsigned i;
+ unsigned i, j;
const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@@ -144,7 +97,6 @@ void __init davinci_irq_init(void)
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
- unsigned j;
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@@ -152,13 +104,8 @@ void __init davinci_irq_init(void)
davinci_irq_writel(pri, i);
}
- /* set up genirq dispatch for ARM INTC */
- for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
- irq_set_chip(i, &davinci_irq_chip_0);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- if (i != IRQ_TINT1_TINT34)
- irq_set_handler(i, handle_edge_irq);
- else
- irq_set_handler(i, handle_level_irq);
- }
+ for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
+ davinci_alloc_gc(davinci_intc_base + j, i, 32);
+
+ irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
}
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