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| author | Sekhar Nori <nsekhar@ti.com> | 2009-11-16 17:21:35 +0530 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-02-04 13:29:36 -0800 |
| commit | c94fa15ba2d736af786ac1e56686d41987b1aba0 (patch) | |
| tree | fa3143cd1ea6029180ee3a69359c05aea9481558 /arch/arm/mach-davinci/psc.c | |
| parent | 7ec4b24326ec9b0467ab23b0417ec6b63e8e5524 (diff) | |
| download | op-kernel-dev-c94fa15ba2d736af786ac1e56686d41987b1aba0.zip op-kernel-dev-c94fa15ba2d736af786ac1e56686d41987b1aba0.tar.gz | |
davinci: move PSC register definitions from psc.c to psc.h
The motivation behind the change is to use the same
definitions in the assembly code responsible for
suspending the SoC, a part of which is to clock gate
the DDR2 clock.
Note that the assembly code cannot invoke the C function
meant for this. The main reason being that stack in DDR2
cannot be accessed while DDR2 clock is being clock gated.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/psc.c')
| -rw-r--r-- | arch/arm/mach-davinci/psc.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 04a3cb7..adf6b5c 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -25,17 +25,6 @@ #include <mach/cputype.h> #include <mach/psc.h> -/* PSC register offsets */ -#define EPCPR 0x070 -#define PTCMD 0x120 -#define PTSTAT 0x128 -#define PDSTAT 0x200 -#define PDCTL1 0x304 -#define MDSTAT 0x800 -#define MDCTL 0xA00 - -#define MDSTAT_STATE_MASK 0x1f - /* Return nonzero iff the domain's clock is active */ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) { |
