diff options
author | Arnd Bergmann <arnd@arndb.de> | 2015-01-30 10:45:33 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2015-12-01 21:52:51 +0100 |
commit | 3acf731ccad039d91721b6cd9fc85569e9f958ca (patch) | |
tree | 37ccacb1c2ebc2519d70dab7e48f7d2961cd0195 /arch/arm/mach-davinci/include | |
parent | d8b2823e950cd9634eb4a01f563ee55afb39d549 (diff) | |
download | op-kernel-dev-3acf731ccad039d91721b6cd9fc85569e9f958ca.zip op-kernel-dev-3acf731ccad039d91721b6cd9fc85569e9f958ca.tar.gz |
ARM: davinci: make headers more local
Some header files are never included outside of a mach-davinci
directory and do not need to be made visible in include/mach,
so let's just move them all down one level.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci/include')
-rw-r--r-- | arch/arm/mach-davinci/include/mach/cp_intc.h | 57 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/cpuidle.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/ddr2.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/psc.h | 217 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/sram.h | 30 |
5 files changed, 0 insertions, 326 deletions
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h deleted file mode 100644 index 827bbe9..0000000 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * TI Common Platform Interrupt Controller (cp_intc) definitions - * - * Author: Steve Chen <schen@mvista.com> - * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -#ifndef __ASM_HARDWARE_CP_INTC_H -#define __ASM_HARDWARE_CP_INTC_H - -#define CP_INTC_REV 0x00 -#define CP_INTC_CTRL 0x04 -#define CP_INTC_HOST_CTRL 0x0C -#define CP_INTC_GLOBAL_ENABLE 0x10 -#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C -#define CP_INTC_SYS_STAT_IDX_SET 0x20 -#define CP_INTC_SYS_STAT_IDX_CLR 0x24 -#define CP_INTC_SYS_ENABLE_IDX_SET 0x28 -#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C -#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30 -#define CP_INTC_HOST_ENABLE_IDX_SET 0x34 -#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38 -#define CP_INTC_PACING_PRESCALE 0x40 -#define CP_INTC_VECTOR_BASE 0x50 -#define CP_INTC_VECTOR_SIZE 0x54 -#define CP_INTC_VECTOR_NULL 0x58 -#define CP_INTC_PRIO_IDX 0x80 -#define CP_INTC_PRIO_VECTOR 0x84 -#define CP_INTC_SECURE_ENABLE 0x90 -#define CP_INTC_SECURE_PRIO_IDX 0x94 -#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4)) -#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4)) -#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4)) -#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2)) -#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) -#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2)) -#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) -#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) -#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2)) -#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2)) -#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) -#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) -#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2)) -#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2)) -#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2)) -#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2)) -#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) -#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) -#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) - -void cp_intc_init(void); -int cp_intc_of_init(struct device_node *, struct device_node *); - -#endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/arch/arm/mach-davinci/include/mach/cpuidle.h b/arch/arm/mach-davinci/include/mach/cpuidle.h deleted file mode 100644 index 74f088b..0000000 --- a/arch/arm/mach-davinci/include/mach/cpuidle.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * TI DaVinci cpuidle platform support - * - * 2009 (C) Texas Instruments, Inc. http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -#ifndef _MACH_DAVINCI_CPUIDLE_H -#define _MACH_DAVINCI_CPUIDLE_H - -struct davinci_cpuidle_config { - u32 ddr2_pdown; - void __iomem *ddr2_ctlr_base; -}; - -#endif diff --git a/arch/arm/mach-davinci/include/mach/ddr2.h b/arch/arm/mach-davinci/include/mach/ddr2.h deleted file mode 100644 index c19e047..0000000 --- a/arch/arm/mach-davinci/include/mach/ddr2.h +++ /dev/null @@ -1,4 +0,0 @@ -#define DDR2_SDRCR_OFFSET 0xc -#define DDR2_SRPD_BIT (1 << 23) -#define DDR2_MCLKSTOPEN_BIT (1 << 30) -#define DDR2_LPMODEN_BIT (1 << 31) diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h deleted file mode 100644 index 99d47cf..0000000 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * DaVinci Power & Sleep Controller (PSC) defines - * - * Copyright (C) 2006 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#ifndef __ASM_ARCH_PSC_H -#define __ASM_ARCH_PSC_H - -#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 - -/* Power and Sleep Controller (PSC) Domains */ -#define DAVINCI_GPSC_ARMDOMAIN 0 -#define DAVINCI_GPSC_DSPDOMAIN 1 - -#define DAVINCI_LPSC_VPSSMSTR 0 -#define DAVINCI_LPSC_VPSSSLV 1 -#define DAVINCI_LPSC_TPCC 2 -#define DAVINCI_LPSC_TPTC0 3 -#define DAVINCI_LPSC_TPTC1 4 -#define DAVINCI_LPSC_EMAC 5 -#define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_USB 9 -#define DAVINCI_LPSC_ATA 10 -#define DAVINCI_LPSC_VLYNQ 11 -#define DAVINCI_LPSC_UHPI 12 -#define DAVINCI_LPSC_DDR_EMIF 13 -#define DAVINCI_LPSC_AEMIF 14 -#define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_McBSP 17 -#define DAVINCI_LPSC_I2C 18 -#define DAVINCI_LPSC_UART0 19 -#define DAVINCI_LPSC_UART1 20 -#define DAVINCI_LPSC_UART2 21 -#define DAVINCI_LPSC_SPI 22 -#define DAVINCI_LPSC_PWM0 23 -#define DAVINCI_LPSC_PWM1 24 -#define DAVINCI_LPSC_PWM2 25 -#define DAVINCI_LPSC_GPIO 26 -#define DAVINCI_LPSC_TIMER0 27 -#define DAVINCI_LPSC_TIMER1 28 -#define DAVINCI_LPSC_TIMER2 29 -#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_LPSC_ARM 31 -#define DAVINCI_LPSC_SCR2 32 -#define DAVINCI_LPSC_SCR3 33 -#define DAVINCI_LPSC_SCR4 34 -#define DAVINCI_LPSC_CROSSBAR 35 -#define DAVINCI_LPSC_CFG27 36 -#define DAVINCI_LPSC_CFG3 37 -#define DAVINCI_LPSC_CFG5 38 -#define DAVINCI_LPSC_GEM 39 -#define DAVINCI_LPSC_IMCOP 40 - -#define DM355_LPSC_TIMER3 5 -#define DM355_LPSC_SPI1 6 -#define DM355_LPSC_MMC_SD1 7 -#define DM355_LPSC_McBSP1 8 -#define DM355_LPSC_PWM3 10 -#define DM355_LPSC_SPI2 11 -#define DM355_LPSC_RTO 12 -#define DM355_LPSC_VPSS_DAC 41 - -/* DM365 */ -#define DM365_LPSC_TIMER3 5 -#define DM365_LPSC_SPI1 6 -#define DM365_LPSC_MMC_SD1 7 -#define DM365_LPSC_McBSP1 8 -#define DM365_LPSC_PWM3 10 -#define DM365_LPSC_SPI2 11 -#define DM365_LPSC_RTO 12 -#define DM365_LPSC_TIMER4 17 -#define DM365_LPSC_SPI0 22 -#define DM365_LPSC_SPI3 38 -#define DM365_LPSC_SPI4 39 -#define DM365_LPSC_EMAC 40 -#define DM365_LPSC_VOICE_CODEC 44 -#define DM365_LPSC_DAC_CLK 46 -#define DM365_LPSC_VPSSMSTR 47 -#define DM365_LPSC_MJCP 50 - -/* - * LPSC Assignments - */ -#define DM646X_LPSC_ARM 0 -#define DM646X_LPSC_C64X_CPU 1 -#define DM646X_LPSC_HDVICP0 2 -#define DM646X_LPSC_HDVICP1 3 -#define DM646X_LPSC_TPCC 4 -#define DM646X_LPSC_TPTC0 5 -#define DM646X_LPSC_TPTC1 6 -#define DM646X_LPSC_TPTC2 7 -#define DM646X_LPSC_TPTC3 8 -#define DM646X_LPSC_PCI 13 -#define DM646X_LPSC_EMAC 14 -#define DM646X_LPSC_VDCE 15 -#define DM646X_LPSC_VPSSMSTR 16 -#define DM646X_LPSC_VPSSSLV 17 -#define DM646X_LPSC_TSIF0 18 -#define DM646X_LPSC_TSIF1 19 -#define DM646X_LPSC_DDR_EMIF 20 -#define DM646X_LPSC_AEMIF 21 -#define DM646X_LPSC_McASP0 22 -#define DM646X_LPSC_McASP1 23 -#define DM646X_LPSC_CRGEN0 24 -#define DM646X_LPSC_CRGEN1 25 -#define DM646X_LPSC_UART0 26 -#define DM646X_LPSC_UART1 27 -#define DM646X_LPSC_UART2 28 -#define DM646X_LPSC_PWM0 29 -#define DM646X_LPSC_PWM1 30 -#define DM646X_LPSC_I2C 31 -#define DM646X_LPSC_SPI 32 -#define DM646X_LPSC_GPIO 33 -#define DM646X_LPSC_TIMER0 34 -#define DM646X_LPSC_TIMER1 35 -#define DM646X_LPSC_ARM_INTC 45 - -/* PSC0 defines */ -#define DA8XX_LPSC0_TPCC 0 -#define DA8XX_LPSC0_TPTC0 1 -#define DA8XX_LPSC0_TPTC1 2 -#define DA8XX_LPSC0_EMIF25 3 -#define DA8XX_LPSC0_SPI0 4 -#define DA8XX_LPSC0_MMC_SD 5 -#define DA8XX_LPSC0_AINTC 6 -#define DA8XX_LPSC0_ARM_RAM_ROM 7 -#define DA8XX_LPSC0_SECU_MGR 8 -#define DA8XX_LPSC0_UART0 9 -#define DA8XX_LPSC0_SCR0_SS 10 -#define DA8XX_LPSC0_SCR1_SS 11 -#define DA8XX_LPSC0_SCR2_SS 12 -#define DA8XX_LPSC0_PRUSS 13 -#define DA8XX_LPSC0_ARM 14 -#define DA8XX_LPSC0_GEM 15 - -/* PSC1 defines */ -#define DA850_LPSC1_TPCC1 0 -#define DA8XX_LPSC1_USB20 1 -#define DA8XX_LPSC1_USB11 2 -#define DA8XX_LPSC1_GPIO 3 -#define DA8XX_LPSC1_UHPI 4 -#define DA8XX_LPSC1_CPGMAC 5 -#define DA8XX_LPSC1_EMIF3C 6 -#define DA8XX_LPSC1_McASP0 7 -#define DA830_LPSC1_McASP1 8 -#define DA850_LPSC1_SATA 8 -#define DA830_LPSC1_McASP2 9 -#define DA850_LPSC1_VPIF 9 -#define DA8XX_LPSC1_SPI1 10 -#define DA8XX_LPSC1_I2C 11 -#define DA8XX_LPSC1_UART1 12 -#define DA8XX_LPSC1_UART2 13 -#define DA8XX_LPSC1_LCDC 16 -#define DA8XX_LPSC1_PWM 17 -#define DA850_LPSC1_MMC_SD1 18 -#define DA8XX_LPSC1_ECAP 20 -#define DA830_LPSC1_EQEP 21 -#define DA850_LPSC1_TPTC2 21 -#define DA8XX_LPSC1_SCR_P0_SS 24 -#define DA8XX_LPSC1_SCR_P1_SS 25 -#define DA8XX_LPSC1_CR_P3_SS 26 -#define DA8XX_LPSC1_L3_CBA_RAM 31 - -/* PSC register offsets */ -#define EPCPR 0x070 -#define PTCMD 0x120 -#define PTSTAT 0x128 -#define PDSTAT 0x200 -#define PDCTL 0x300 -#define MDSTAT 0x800 -#define MDCTL 0xA00 - -/* PSC module states */ -#define PSC_STATE_SWRSTDISABLE 0 -#define PSC_STATE_SYNCRST 1 -#define PSC_STATE_DISABLE 2 -#define PSC_STATE_ENABLE 3 - -#define MDSTAT_STATE_MASK 0x3f -#define PDSTAT_STATE_MASK 0x1f -#define MDCTL_LRST BIT(8) -#define MDCTL_FORCE BIT(31) -#define PDCTL_NEXT BIT(0) -#define PDCTL_EPCGOOD BIT(8) - -#ifndef __ASSEMBLER__ - -extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); -extern void davinci_psc_reset(unsigned int ctlr, unsigned int id, - bool reset); -extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, bool enable, u32 flags); - -#endif - -#endif /* __ASM_ARCH_PSC_H */ diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h deleted file mode 100644 index 4e5db56..0000000 --- a/arch/arm/mach-davinci/include/mach/sram.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * mach/sram.h - DaVinci simple SRAM allocator - * - * Copyright (C) 2009 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MACH_SRAM_H -#define __MACH_SRAM_H - -/* ARBITRARY: SRAM allocations are multiples of this 2^N size */ -#define SRAM_GRANULARITY 512 - -/* - * SRAM allocations return a CPU virtual address, or NULL on error. - * If a DMA address is requested and the SRAM supports DMA, its - * mapped address is also returned. - * - * Errors include SRAM memory not being available, and requesting - * DMA mapped SRAM on systems which don't allow that. - */ -extern void *sram_alloc(size_t len, dma_addr_t *dma); -extern void sram_free(void *addr, size_t len); - -/* Get the struct gen_pool * for use in platform data */ -extern struct gen_pool *sram_get_gen_pool(void); - -#endif /* __MACH_SRAM_H */ |