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| author | Sekhar Nori <nsekhar@ti.com> | 2010-08-09 15:46:35 +0530 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-09-24 07:40:26 -0700 |
| commit | 8060ef4da9e73f461adf2ba1922ea5400a61cf98 (patch) | |
| tree | c2b32a3ba886a40803aba15dd6f52852e912b846 /arch/arm/mach-davinci/include/mach/nand.h | |
| parent | 13d36a923da6a1e0584e07d91320373c790c01c3 (diff) | |
| download | op-kernel-dev-8060ef4da9e73f461adf2ba1922ea5400a61cf98.zip op-kernel-dev-8060ef4da9e73f461adf2ba1922ea5400a61cf98.tar.gz | |
davinci: add support for aemif timing configuration
This patch adds support to configure the AEMIF interface
with supplied timing values.
Since this capability is useful both from NOR and NAND
flashes, it is provided as a new interface and in a file
of its own.
AEMIF timing configuration is required in cases:
1) Where the AEMIF clock rate can change at runtime (a side
affect of cpu frequency change).
2) Where U-Boot does not support NAND/NOR but supports other
media like SPI Flash or MMC/SD and thus does not care about
setting up the AEMIF timing for kernel to use.
3) Where U-Boot just hasn't configured the timing values and
cannot be upgraded because the box is already in the field.
Since there is now a header file for AEMIF interface, the
common (non-NAND specific) defines for AEMIF registers have
been moved from nand.h into the newly created aemif.h
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/include/mach/nand.h')
| -rw-r--r-- | arch/arm/mach-davinci/include/mach/nand.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b2ad809..b5893f0 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -30,9 +30,6 @@ #include <linux/mtd/nand.h> -#define NRCSR_OFFSET 0x00 -#define AWCCR_OFFSET 0x04 -#define A1CR_OFFSET 0x10 #define NANDFCR_OFFSET 0x60 #define NANDFSR_OFFSET 0x64 #define NANDF1ECC_OFFSET 0x70 |
