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authorCyril Chemparathy <cyril@ti.com>2010-05-01 18:38:27 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-06 15:02:09 -0700
commit5b3a05ca911688c53680f2b020a1512b9da29c89 (patch)
tree4724dd98e7ef949d1976865ad1198c8693d341da /arch/arm/mach-davinci/gpio.c
parentb27b6d03f245e5eaf6473da58a2612077fb7cfe7 (diff)
downloadop-kernel-dev-5b3a05ca911688c53680f2b020a1512b9da29c89.zip
op-kernel-dev-5b3a05ca911688c53680f2b020a1512b9da29c89.tar.gz
Davinci: eliminate pinmux offset verbosity
Pinmux registers are sequential, and do not need to be enumerated out as they currently are. This reduces code volume and keeps things simple. If some future SoC comes up with a discontiguous register map, PINMUX() can then be expanded with local token pasting. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/gpio.c')
-rw-r--r--arch/arm/mach-davinci/gpio.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b62d5e2..2efb446 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -71,11 +71,7 @@ static int __init davinci_gpio_irq_setup(void);
/*--------------------------------------------------------------------------*/
-/*
- * board setup code *MUST* set PINMUX0 and PINMUX1 as
- * needed, and enable the GPIO clock.
- */
-
+/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out, int value)
{
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