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author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-08-23 13:44:43 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-08-23 13:44:43 -0700 |
commit | 9e259f9352d52053058a234f7c062c4e4f56dc85 (patch) | |
tree | bfb1c442e27f95ddb9a04bae2a44ca9e3dd69a85 /arch/arm/mach-davinci/clock.h | |
parent | 5563ae9b39c5ba492be1b18f2d72fd43ba549915 (diff) | |
parent | f0fc40aff6fee100ffbed8328a0df88f8aa75fce (diff) | |
download | op-kernel-dev-9e259f9352d52053058a234f7c062c4e4f56dc85.zip op-kernel-dev-9e259f9352d52053058a234f7c062c4e4f56dc85.tar.gz |
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 32-bit SoC platform updates from Olof Johansson:
"Most of the SoC updates in this cycle are cleanups and moves to more
modern infrastructure:
- Davinci was moved to common clock framework
- OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the
keyboard interface (bitbanged AT keyboard via GPIO).
- Removal of some stale code for Renesas platforms
- Power management improvements for i.MX6LL"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (112 commits)
ARM: uniphier: select RESET_CONTROLLER
arm64: uniphier: select RESET_CONTROLLER
ARM: uniphier: remove empty Makefile
ARM: exynos: Clear global variable on init error path
ARM: exynos: Remove outdated maintainer information
ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15
ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill
soc: r9a06g032: don't build SMP files for non-SMP config
ARM: shmobile: Add the R9A06G032 SMP enabler driver
ARM: at91: pm: configure wakeup sources for ULP1 mode
ARM: at91: pm: add PMC fast startup registers defines
ARM: at91: pm: Add ULP1 mode support
ARM: at91: pm: Use ULP0 naming instead of slow clock
ARM: hisi: handle of_iomap and fix missing of_node_put
ARM: hisi: check of_iomap and fix missing of_node_put
ARM: hisi: fix error handling and missing of_node_put
ARM: mx5: Set the DBGEN bit in ARM_GPC register
ARM: imx51: Configure M4IF to avoid visual artifacts
ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll
ARM: imx: fix i.MX6SLL build
...
Diffstat (limited to 'arch/arm/mach-davinci/clock.h')
-rw-r--r-- | arch/arm/mach-davinci/clock.h | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index d7894d5..3073834 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -12,10 +12,6 @@ #ifndef __ARCH_ARM_DAVINCI_CLOCK_H #define __ARCH_ARM_DAVINCI_CLOCK_H -#define DAVINCI_PLL1_BASE 0x01c40800 -#define DAVINCI_PLL2_BASE 0x01c40c00 -#define MAX_PLL 2 - /* PLL/Reset register offsets */ #define PLLCTL 0x100 #define PLLCTL_PLLEN BIT(0) @@ -65,76 +61,4 @@ */ #define PLL_LOCK_TIME 20 -#ifndef __ASSEMBLER__ - -#include <linux/list.h> -#include <linux/clkdev.h> - -#define PLLSTAT_GOSTAT BIT(0) -#define PLLCMD_GOSET BIT(0) - -struct pll_data { - u32 phys_base; - void __iomem *base; - u32 num; - u32 flags; - u32 input_rate; - u32 div_ratio_mask; -}; -#define PLL_HAS_PREDIV 0x01 -#define PLL_HAS_POSTDIV 0x02 - -struct clk { - struct list_head node; - struct module *owner; - const char *name; - unsigned long rate; - unsigned long maxrate; /* H/W supported max rate */ - u8 usecount; - u8 lpsc; - u8 gpsc; - u8 domain; - u32 flags; - struct clk *parent; - struct list_head children; /* list of children */ - struct list_head childnode; /* parent's child list node */ - struct pll_data *pll_data; - u32 div_reg; - unsigned long (*recalc) (struct clk *); - int (*set_rate) (struct clk *clk, unsigned long rate); - int (*round_rate) (struct clk *clk, unsigned long rate); - int (*reset) (struct clk *clk, bool reset); - void (*clk_enable) (struct clk *clk); - void (*clk_disable) (struct clk *clk); - int (*set_parent) (struct clk *clk, struct clk *parent); -}; - -/* Clock flags: SoC-specific flags start at BIT(16) */ -#define ALWAYS_ENABLED BIT(1) -#define CLK_PSC BIT(2) -#define CLK_PLL BIT(3) /* PLL-derived clock */ -#define PRE_PLL BIT(4) /* source is before PLL mult/div */ -#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ -#define PSC_FORCE BIT(6) /* Force module state transtition */ -#define PSC_LRST BIT(8) /* Use local reset on enable/disable */ - -#define CLK(dev, con, ck) \ - { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - } \ - -int davinci_clk_init(struct clk_lookup *clocks); -int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, - unsigned int mult, unsigned int postdiv); -int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); -int davinci_set_refclk_rate(unsigned long rate); -int davinci_simple_set_rate(struct clk *clk, unsigned long rate); -int davinci_clk_reset(struct clk *clk, bool reset); -void davinci_clk_enable(struct clk *clk); -void davinci_clk_disable(struct clk *clk); - -#endif - #endif |