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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-03-02 20:54:37 +0800
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-03-15 23:37:56 +0800
commita7776ec625c8ca90d050953946a5b72eaf41c21c (patch)
treecc2717698bc80e5511b06fa83936f0fd9617aa9c /arch/arm/mach-at91/setup.c
parentc8082d344ac4c05932fec1766e5e9ce72cf286ed (diff)
downloadop-kernel-dev-a7776ec625c8ca90d050953946a5b72eaf41c21c.zip
op-kernel-dev-a7776ec625c8ca90d050953946a5b72eaf41c21c.tar.gz
ARM: at91: add ram controller DT support
We can now drop the call to ioremap_registers() as we have the binding for the SDRAM/DDR Controller. Drop ioremap_registers() for sam9x5 too. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/setup.c')
-rw-r--r--arch/arm/mach-at91/setup.c40
1 files changed, 37 insertions, 3 deletions
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 3e48b59..46d0a56 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -52,6 +52,19 @@ void __init at91_init_interrupts(unsigned int *priority)
at91_gpio_irq_setup();
}
+void __iomem *at91_ramc_base[2];
+
+void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
+{
+ if (id < 0 || id > 1) {
+ pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
+ BUG();
+ }
+ at91_ramc_base[id] = ioremap(addr, size);
+ if (!at91_ramc_base[id])
+ panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
+}
+
static struct map_desc sram_desc[2] __initdata;
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
@@ -315,12 +328,33 @@ static void at91_dt_rstc(void)
of_node_put(np);
}
+static struct of_device_id ramc_ids[] = {
+ { .compatible = "atmel,at91sam9260-sdramc" },
+ { .compatible = "atmel,at91sam9g45-ddramc" },
+ { /*sentinel*/ }
+};
+
+static void at91_dt_ramc(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, ramc_ids);
+ if (!np)
+ panic("unable to find compatible ram conroller node in dtb\n");
+
+ at91_ramc_base[0] = of_iomap(np, 0);
+ if (!at91_ramc_base[0])
+ panic("unable to map ramc[0] cpu registers\n");
+ /* the controller may have 2 banks */
+ at91_ramc_base[1] = of_iomap(np, 1);
+
+ of_node_put(np);
+}
+
void __init at91_dt_initialize(void)
{
at91_dt_rstc();
-
- /* temporary until have the ramc binding*/
- at91_boot_soc.ioremap_registers();
+ at91_dt_ramc();
/* Init clock subsystem */
at91_dt_clock_init();
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