Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull support for new arm SoCs from Olof Johansson:
 "Three new system-on-chip models are supported: the st-ericsson u9540
  in ux500, the sam9n12 in at91 and the emma ev2 in shmobile.

  Emma is a little bit special because it is completely unrelated to the
  classic shmobile models, but the new Renesas rmobile SoCs are a
  combination of things from both Emma and shmobile, so it was decided
  to have them all live in one directory.

  This also contains updates to existing shmobile soc code as well as
  some related board changes due to dependencies."

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
  mach-shmobile: Use DT_MACHINE for KZM9D V3
  mach-shmobile: Emma Mobile EV2 DT support V3
  mach-shmobile: KZM9D board Ethernet support V3
  mach-shmobile: Emma Mobile EV2 GPIO support V3
  mach-shmobile: Emma Mobile EV2 SMP support V3
  mach-shmobile: KZM9D board support V3
  mach-shmobile: Emma Mobile EV2 SoC base support V3
  gpio: Emma Mobile GPIO driver V2
  ARM: mach-shmobile: sh73a0: fixup PINT/IRQ16-IRQ31 irq number conflict
  ARM: mach-shmobile: clock-r8a7740: use followparent_recalc on usb24s
  ARM: mach-shmobile: clock-r8a7740: add MMCIF clock
  ARM: mach-shmobile: clock-r8a7740: add SDHI clock
  ARM: mach-shmobile: clock-r8a7740: add USB clock
  ARM: mach-shmobile: clock-r8a7740: add FSI clock
  ARM: mach-shmobile: r8a7740: cleanup I2C workaround method
  ARM: mach-shmobile: r8a7740: add gpio_irq support
  ARM: mach-shmobile: sh7372: Add FSI DMAEngine support
  ARM / mach-shmobile: Use preset_lpj with calibrate_delay()
  ARM: ux500: ioremap differences for DB9540
  ARM: ux500: core U9540 support
  ...

1 files changed, 60 insertions, 0 deletions

diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
new file mode 100644
index 0000000..d374b87
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -0,0 +1,60 @@
+/*
+ * SoC specific header file for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * Common definitions, based on AT91SAM9N12 SoC datasheet
+ *
+ * Licensed under GPLv2 or later
+ */
+
+#ifndef _AT91SAM9N12_H_
+#define _AT91SAM9N12_H_
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91SAM9N12_ID_PIOAB	2	/* Parallel I/O Controller A and B */
+#define AT91SAM9N12_ID_PIOCD	3	/* Parallel I/O Controller C and D */
+#define AT91SAM9N12_ID_FUSE	4	/* FUSE Controller */
+#define AT91SAM9N12_ID_USART0	5	/* USART 0 */
+#define AT91SAM9N12_ID_USART1	6	/* USART 1 */
+#define AT91SAM9N12_ID_USART2	7	/* USART 2 */
+#define AT91SAM9N12_ID_USART3	8	/* USART 3 */
+#define AT91SAM9N12_ID_TWI0	9	/* Two-Wire Interface 0 */
+#define AT91SAM9N12_ID_TWI1	10	/* Two-Wire Interface 1 */
+#define AT91SAM9N12_ID_MCI	12	/* High Speed Multimedia Card Interface */
+#define AT91SAM9N12_ID_SPI0	13	/* Serial Peripheral Interface 0 */
+#define AT91SAM9N12_ID_SPI1	14	/* Serial Peripheral Interface 1 */
+#define AT91SAM9N12_ID_UART0	15	/* UART 0 */
+#define AT91SAM9N12_ID_UART1	16	/* UART 1 */
+#define AT91SAM9N12_ID_TCB	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9N12_ID_PWM	18	/* Pulse Width Modulation Controller */
+#define AT91SAM9N12_ID_ADC	19	/* ADC Controller */
+#define AT91SAM9N12_ID_DMA	20	/* DMA Controller */
+#define AT91SAM9N12_ID_UHP	22	/* USB Host High Speed */
+#define AT91SAM9N12_ID_UDP	23	/* USB Device High Speed */
+#define AT91SAM9N12_ID_LCDC	25	/* LCD Controller */
+#define AT91SAM9N12_ID_ISI	25	/* Image Sensor Interface */
+#define AT91SAM9N12_ID_SSC	28	/* Synchronous Serial Controller */
+#define AT91SAM9N12_ID_TRNG	30	/* TRNG */
+#define AT91SAM9N12_ID_IRQ0	31	/* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9N12_BASE_USART0	0xf801c000
+#define AT91SAM9N12_BASE_USART1	0xf8020000
+#define AT91SAM9N12_BASE_USART2	0xf8024000
+#define AT91SAM9N12_BASE_USART3	0xf8028000
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9N12_SRAM_BASE	0x00300000	/* Internal SRAM base address */
+#define AT91SAM9N12_SRAM_SIZE	SZ_32K		/* Internal SRAM size (32Kb) */
+
+#define AT91SAM9N12_ROM_BASE	0x00100000	/* Internal ROM base address */
+#define AT91SAM9N12_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */
+
+#endif