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| author | Marc Zyngier <Marc.Zyngier@arm.com> | 2012-01-20 12:24:47 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-23 10:20:07 +0000 |
| commit | c214455f3205fa20819da6d67a8b20609ff786e7 (patch) | |
| tree | cd3a1f9557007ff899ecdd17d1a1f0cc3fd88483 /arch/arm/kernel | |
| parent | 612539e81f655f6ac73c7af1da8701c1ee618aee (diff) | |
| download | op-kernel-dev-c214455f3205fa20819da6d67a8b20609ff786e7.zip op-kernel-dev-c214455f3205fa20819da6d67a8b20609ff786e7.tar.gz | |
ARM: 7297/1: smp_twd: make sure timer is stopped before registering it
On secondary CPUs, the Timer Control Register is not reset
to a sane value before the timer is registered, and the TRM
doesn't seem to indicate any reset value either. In some cases,
the kernel will take an interrupt too early, depending on what
junk was present in the registers at reset time.
The fix is to set the Timer Control Register to 0 before
registering the clock_event_device and enabling the interrupt.
Problem seen on VE (Cortex A5) and Tegra.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/smp_twd.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index c8e9385..4285daa 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) else twd_calibrate_rate(); + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); + clk->name = "local_timer"; clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP; |
