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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-02-04 10:55:38 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-03-24 09:38:52 +0000 |
| commit | 87067a935a174cf5e0b336d338a0ab535ffe199d (patch) | |
| tree | 03a56144e82fb7bfded621e6b291906608aa1d81 /arch/arm/kernel/traps.c | |
| parent | d9277d51a8eeaa097d3c1385f458c99d65ffc4f4 (diff) | |
| download | op-kernel-dev-87067a935a174cf5e0b336d338a0ab535ffe199d.zip op-kernel-dev-87067a935a174cf5e0b336d338a0ab535ffe199d.tar.gz | |
ARM: Optimize multi-CPU tlb flushing a little more
The compiler does not conditionalize the assembly instructions for
the tlb operations, which leads to sub-optimal code being generated
when building a kernel for multiple CPUs.
We can tweak things fairly simply as the code fragment below shows:
17f8: e3120001 tst r2, #1 ; 0x1
...
1800: 0a000000 beq 1808 <handle_pte_fault+0x194>
1804: ee061f10 mcr 15, 0, r1, cr6, cr0, {0}
1808: e3120004 tst r2, #4 ; 0x4
180c: 0a000000 beq 1814 <handle_pte_fault+0x1a0>
1810: ee081f36 mcr 15, 0, r1, cr8, cr6, {1}
becomes:
17f0: e3120001 tst r2, #1 ; 0x1
17f4: 1e063f10 mcrne 15, 0, r3, cr6, cr0, {0}
17f8: e3120004 tst r2, #4 ; 0x4
17fc: 1e083f36 mcrne 15, 0, r3, cr8, cr6, {1}
Overall, for Realview with V6 and V7 CPUs configured:
text data bss dec hex filename
4153998 207340 5371036 9732374 948116 ../build/realview/vmlinux.before
4153366 207332 5371036 9731734 947e96 ../build/realview/vmlinux.after
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/traps.c')
0 files changed, 0 insertions, 0 deletions
