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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-10-19 13:02:47 -0700
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-10-19 13:02:47 -0700
commitdfc568e6bc08916f1035af456e4631c47166b5cf (patch)
tree3c96bdc26687e0f6958e790c8c93c0c6efb6b8d6 /arch/arm/kernel/head.S
parentfdf91dae6f024c6dfee425fe754df6b1957f6c53 (diff)
parent31d141e3a666269a3b6fcccddb0351caf7454240 (diff)
downloadop-kernel-dev-dfc568e6bc08916f1035af456e4631c47166b5cf.zip
op-kernel-dev-dfc568e6bc08916f1035af456e4631c47166b5cf.tar.gz
Merge 3.12-rc6 into char-misc-next
We want the fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/kernel/head.S')
-rw-r--r--arch/arm/kernel/head.S21
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 2c7cc1e..476de57 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -487,7 +487,26 @@ __fixup_smp:
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
and r0, r0, #0xc0000000 @ multiprocessing extensions and
teq r0, #0x80000000 @ not part of a uniprocessor system?
- moveq pc, lr @ yes, assume SMP
+ bne __fixup_smp_on_up @ no, assume UP
+
+ @ Core indicates it is SMP. Check for Aegis SOC where a single
+ @ Cortex-A9 CPU is present but SMP operations fault.
+ mov r4, #0x41000000
+ orr r4, r4, #0x0000c000
+ orr r4, r4, #0x00000090
+ teq r3, r4 @ Check for ARM Cortex-A9
+ movne pc, lr @ Not ARM Cortex-A9,
+
+ @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
+ @ below address check will need to be #ifdef'd or equivalent
+ @ for the Aegis platform.
+ mrc p15, 4, r0, c15, c0 @ get SCU base address
+ teq r0, #0x0 @ '0' on actual UP A9 hardware
+ beq __fixup_smp_on_up @ So its an A9 UP
+ ldr r0, [r0, #4] @ read SCU Config
+ and r0, r0, #0x3 @ number of CPUs
+ teq r0, #0x0 @ is 1?
+ movne pc, lr
__fixup_smp_on_up:
adr r0, 1f
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