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authorCatalin Marinas <catalin.marinas@arm.com>2008-08-28 11:22:32 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-09-01 12:06:34 +0100
commit93ed3970114983543bbebd195bef65db84444ea2 (patch)
tree9df88b61a2a7b3cc493c6cfc5f4848448250f6b5 /arch/arm/kernel/entry-armv.S
parent8d5796d2ec6b5a4e7a52861144e63af438d6f8f7 (diff)
downloadop-kernel-dev-93ed3970114983543bbebd195bef65db84444ea2.zip
op-kernel-dev-93ed3970114983543bbebd195bef65db84444ea2.tar.gz
[ARM] 5227/1: Add the ENDPROC declarations to the .S files
This declaration specifies the "function" type and size for various assembly functions, mainly needed for generating the correct branch instructions in Thumb-2. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/entry-armv.S')
-rw-r--r--arch/arm/kernel/entry-armv.S16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 617e509..77b0474 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -76,14 +76,17 @@
__pabt_invalid:
inv_entry BAD_PREFETCH
b common_invalid
+ENDPROC(__pabt_invalid)
__dabt_invalid:
inv_entry BAD_DATA
b common_invalid
+ENDPROC(__dabt_invalid)
__irq_invalid:
inv_entry BAD_IRQ
b common_invalid
+ENDPROC(__irq_invalid)
__und_invalid:
inv_entry BAD_UNDEFINSTR
@@ -107,6 +110,7 @@ common_invalid:
mov r0, sp
b bad_mode
+ENDPROC(__und_invalid)
/*
* SVC mode handlers
@@ -192,6 +196,7 @@ __dabt_svc:
ldr r0, [sp, #S_PSR]
msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
+ENDPROC(__dabt_svc)
.align 5
__irq_svc:
@@ -223,6 +228,7 @@ __irq_svc:
bleq trace_hardirqs_on
#endif
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
+ENDPROC(__irq_svc)
.ltorg
@@ -272,6 +278,7 @@ __und_svc:
ldr lr, [sp, #S_PSR] @ Get SVC cpsr
msr spsr_cxsf, lr
ldmia sp, {r0 - pc}^ @ Restore SVC registers
+ENDPROC(__und_svc)
.align 5
__pabt_svc:
@@ -313,6 +320,7 @@ __pabt_svc:
ldr r0, [sp, #S_PSR]
msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
+ENDPROC(__pabt_svc)
.align 5
.LCcralign:
@@ -412,6 +420,7 @@ __dabt_usr:
mov r2, sp
adr lr, ret_from_exception
b do_DataAbort
+ENDPROC(__dabt_usr)
.align 5
__irq_usr:
@@ -441,6 +450,7 @@ __irq_usr:
mov why, #0
b ret_to_user
+ENDPROC(__irq_usr)
.ltorg
@@ -474,6 +484,7 @@ __und_usr:
#else
b __und_usr_unknown
#endif
+ENDPROC(__und_usr)
@
@ fallthrough to call_fpe
@@ -642,6 +653,7 @@ __und_usr_unknown:
mov r0, sp
adr lr, ret_from_exception
b do_undefinstr
+ENDPROC(__und_usr_unknown)
.align 5
__pabt_usr:
@@ -666,6 +678,8 @@ ENTRY(ret_from_exception)
get_thread_info tsk
mov why, #0
b ret_to_user
+ENDPROC(__pabt_usr)
+ENDPROC(ret_from_exception)
/*
* Register switch for ARMv3 and ARMv4 processors
@@ -702,6 +716,7 @@ ENTRY(__switch_to)
bl atomic_notifier_call_chain
mov r0, r5
ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
+ENDPROC(__switch_to)
__INIT
@@ -1029,6 +1044,7 @@ vector_\name:
mov r0, sp
ldr lr, [pc, lr, lsl #2]
movs pc, lr @ branch to handler in SVC mode
+ENDPROC(vector_\name)
.endm
.globl __stubs_start
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