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author | Kevin Hilman <khilman@linaro.org> | 2013-08-13 15:12:02 -0700 |
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committer | Kevin Hilman <khilman@linaro.org> | 2013-08-13 15:12:20 -0700 |
commit | bee22087faf5bbf33fcb61e6c5e8f8ef7ebd77a5 (patch) | |
tree | 1ca5384ec71f31bd9ae04d867952ca2ced00fe11 /arch/arm/include | |
parent | 311b79bb7e253dc5916db6dc14374dae0cd4ff9c (diff) | |
parent | 3294a7e7c3a55bb4eb9d98b0af5643a7ea44afe1 (diff) | |
download | op-kernel-dev-bee22087faf5bbf33fcb61e6c5e8f8ef7ebd77a5.zip op-kernel-dev-bee22087faf5bbf33fcb61e6c5e8f8ef7ebd77a5.tar.gz |
Merge branch 'msm/cleanup' into next/cleanup
From David Brown <davidb@codeaurora.org>:
* msm/cleanup:
ARM: msm: Only compile io.c on platforms that use it
iommu/msm: Move mach includes to iommu directory
ARM: msm: Remove devices-iommu.c
ARM: msm: Move mach/board.h contents to common.h
ARM: msm: Migrate msm_timer to CLOCKSOURCE_OF_DECLARE
ARM: msm: Remove TMR and TMR0 static mappings
ARM: msm: Move debug-macro.S to include/debug
ARM: msm: Don't compile __msm_ioremap_caller() unless used
ARM: msm: Remove unused and unmapped MSM_TLMM_BASE for 8x60
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/debug/msm.S | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S new file mode 100644 index 0000000..9166e1b --- /dev/null +++ b/arch/arm/include/debug/msm.S @@ -0,0 +1,93 @@ +/* + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50) +#define MSM_UART1_PHYS 0xA9A00000 +#define MSM_UART2_PHYS 0xA9B00000 +#define MSM_UART3_PHYS 0xA9C00000 +#elif defined(CONFIG_ARCH_MSM7X30) +#define MSM_UART1_PHYS 0xACA00000 +#define MSM_UART2_PHYS 0xACB00000 +#define MSM_UART3_PHYS 0xACC00000 +#endif + +#if defined(CONFIG_DEBUG_MSM_UART1) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS +#elif defined(CONFIG_DEBUG_MSM_UART2) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS +#elif defined(CONFIG_DEBUG_MSM_UART3) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS +#endif + +#ifdef CONFIG_DEBUG_MSM8660_UART +#define MSM_DEBUG_UART_BASE 0xF0040000 +#define MSM_DEBUG_UART_PHYS 0x19C40000 +#endif + +#ifdef CONFIG_DEBUG_MSM8960_UART +#define MSM_DEBUG_UART_BASE 0xF0040000 +#define MSM_DEBUG_UART_PHYS 0x16440000 +#endif + + .macro addruart, rp, rv, tmp +#ifdef MSM_DEBUG_UART_PHYS + ldr \rp, =MSM_DEBUG_UART_PHYS + ldr \rv, =MSM_DEBUG_UART_BASE +#endif + .endm + + .macro senduart, rd, rx +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS + @ Write the 1 character to UARTDM_TF + str \rd, [\rx, #0x70] +#else + str \rd, [\rx, #0x0C] +#endif + .endm + + .macro waituart, rd, rx +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS + @ check for TX_EMT in UARTDM_SR + ldr \rd, [\rx, #0x08] + tst \rd, #0x08 + bne 1002f + @ wait for TXREADY in UARTDM_ISR +1001: ldr \rd, [\rx, #0x14] + tst \rd, #0x80 + beq 1001b +1002: + @ Clear TX_READY by writing to the UARTDM_CR register + mov \rd, #0x300 + str \rd, [\rx, #0x10] + @ Write 0x1 to NCF register + mov \rd, #0x1 + str \rd, [\rx, #0x40] + @ UARTDM reg. Read to induce delay + ldr \rd, [\rx, #0x08] +#else + @ wait for TX_READY +1001: ldr \rd, [\rx, #0x08] + tst \rd, #0x04 + beq 1001b +#endif + .endm + + .macro busyuart, rd, rx + .endm |