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authorOlof Johansson <olof@lixom.net>2018-05-14 13:28:11 -0700
committerOlof Johansson <olof@lixom.net>2018-05-14 13:28:11 -0700
commit08a5f1ac35b0a42e4edece0cda2a79d2fe92fa03 (patch)
treebedfcba0a39fc10f614a1ac25ecbce1881c0072c /arch/arm/include/asm
parente5d9875ecd2e75b30d906c480ccc1896948e2d03 (diff)
parent56e4446df9c1214e886fdc7603a5c1cb99cb1843 (diff)
downloadop-kernel-dev-08a5f1ac35b0a42e4edece0cda2a79d2fe92fa03.zip
op-kernel-dev-08a5f1ac35b0a42e4edece0cda2a79d2fe92fa03.tar.gz
Merge tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux into next/soc
This pull request contains Broadcom ARM-based machine/platform files changes for 4.18, please pull the following: - Doug updates arch/arm/include/asm/cpuinfo.h such that this header file can be used by both C and assembly code. This particular change will also be included in a Sunxi pull request to support A83T SMP support. - Doug also updates our DEBUG_LL routine to support newer chips such as 7278 which have a version 7 memory map which moves the registers from physical address 0xf000_0000 down to 0x0800_0000. This requires us to look up the processor MIDR and determine the base address from the PERIPHBASE register. - Florian updates the Brahma-B15 read-ahead cache implementation such that it works on the Brahma-B53 CPUs, which also have an identical read-ahead cache implementation, with a different set of offsets. He also provides the Brahma-B15 MIDR definition such that it can be used by other pieces of code in the future. * tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux: ARM: brcmstb: Add support for the V7 memory map ARM: add Broadcom Brahma-B15 main ID definition ARM: add Broadcom Brahma-B53 main ID definition ARM: Allow this header to be included by assembly files ARM: B15: Update to support Brahma-B53 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/cputype.h15
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb54642..d1b62ee 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,9 +2,6 @@
#ifndef __ASM_ARM_CPUTYPE_H
#define __ASM_ARM_CPUTYPE_H
-#include <linux/stringify.h>
-#include <linux/kernel.h>
-
#define CPUID_ID 0
#define CPUID_CACHETYPE 1
#define CPUID_TCM 2
@@ -62,6 +59,7 @@
((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
#define ARM_CPU_IMP_ARM 0x41
+#define ARM_CPU_IMP_BRCM 0x42
#define ARM_CPU_IMP_DEC 0x44
#define ARM_CPU_IMP_INTEL 0x69
@@ -79,6 +77,10 @@
#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
#define ARM_CPU_PART_MASK 0xff00fff0
+/* Broadcom implemented processors */
+#define ARM_CPU_PART_BRAHMA_B15 0x420000f0
+#define ARM_CPU_PART_BRAHMA_B53 0x42001000
+
/* DEC implemented cores */
#define ARM_CPU_PART_SA1100 0x4400a110
@@ -98,6 +100,11 @@
/* Qualcomm implemented cores */
#define ARM_CPU_PART_SCORPION 0x510002d0
+#ifndef __ASSEMBLY__
+
+#include <linux/stringify.h>
+#include <linux/kernel.h>
+
extern unsigned int processor_id;
#ifdef CONFIG_CPU_CP15
@@ -326,4 +333,6 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
#define cpuid_feature_extract(reg, field) \
cpuid_feature_extract_field(read_cpuid_ext(reg), field)
+#endif /* __ASSEMBLY__ */
+
#endif
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