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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-03-08 06:59:54 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-03-09 00:18:34 +0000 |
| commit | 2839e06c95d12ada034cf9b63da60334c7c6358b (patch) | |
| tree | 9295f80025852f73fbf3c66740eae76df5d61314 /arch/arm/include/asm/outercache.h | |
| parent | d239b1dc093d551046a909920b5310c1d1e308c1 (diff) | |
| download | op-kernel-dev-2839e06c95d12ada034cf9b63da60334c7c6358b.zip op-kernel-dev-2839e06c95d12ada034cf9b63da60334c7c6358b.tar.gz | |
ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.
Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)
This patch also removes any OMAP dependency on PL310 Errata's
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/outercache.h')
| -rw-r--r-- | arch/arm/include/asm/outercache.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index fc19009..348d513 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -31,6 +31,7 @@ struct outer_cache_fns { #ifdef CONFIG_OUTER_CACHE_SYNC void (*sync)(void); #endif + void (*set_debug)(unsigned long); }; #ifdef CONFIG_OUTER_CACHE |
