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| author | Will Deacon <will.deacon@arm.com> | 2011-11-22 17:30:28 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 10:30:38 +0000 |
| commit | d675d0bc47f28c5414fbbe17fcc801f69c45b960 (patch) | |
| tree | 78d7b2c43650d6af96caac9e631409cf15c8f25a /arch/arm/include/asm/assembler.h | |
| parent | 8d2cd3a38fd663bd341507f5ac29002ffd81d986 (diff) | |
| download | op-kernel-dev-d675d0bc47f28c5414fbbe17fcc801f69c45b960.zip op-kernel-dev-d675d0bc47f28c5414fbbe17fcc801f69c45b960.tar.gz | |
ARM: LPAE: add ISBs around MMU enabling code
Before we enable the MMU, we must ensure that the TTBR registers contain
sane values. After the MMU has been enabled, we jump to the *virtual*
address of the following function, so we also need to ensure that the
SCTLR write has taken effect.
This patch adds ISB instructions around the SCTLR write to ensure the
visibility of the above.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/include/asm/assembler.h')
| -rw-r--r-- | arch/arm/include/asm/assembler.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 29035e8..b6e65de 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -187,6 +187,17 @@ #endif /* + * Instruction barrier + */ + .macro instr_sync +#if __LINUX_ARM_ARCH__ >= 7 + isb +#elif __LINUX_ARM_ARCH__ == 6 + mcr p15, 0, r0, c7, c5, 4 +#endif + .endm + +/* * SMP data memory barrier */ .macro smp_dmb mode |
