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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-06-13 00:12:06 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-06-16 09:25:21 +0900 |
| commit | 56efdbe56bc674208d01e3afdfb47f6b5b90da3d (patch) | |
| tree | 5701ec6f2fbe05905feb91dc1c1c9db1f71ac125 /arch/arm/boot | |
| parent | e66796b9bb87d2c48f68e5eb27dcfbc4c26c18d4 (diff) | |
| download | op-kernel-dev-56efdbe56bc674208d01e3afdfb47f6b5b90da3d.zip op-kernel-dev-56efdbe56bc674208d01e3afdfb47f6b5b90da3d.tar.gz | |
ARM: dts: r8a7792: add IRQC support
Describe the IRQC interrupt controller in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index b6e34b4..18b4e50 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -61,6 +61,19 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7792_CLK_IRQC>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |
