summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-26 23:10:11 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-26 23:10:11 +0000
commit542f869f1826f092606efd0c4c771f070d1314f5 (patch)
tree9c9d265ab0c87ea7862ccb70933f33d3d7011334 /arch/arm/boot
parente8b374bb6c888a70530d800c9e2fcd153e2c325d (diff)
parent839e642f3dda44a35c6a91780bff41d84c288022 (diff)
downloadop-kernel-dev-542f869f1826f092606efd0c4c771f070d1314f5.zip
op-kernel-dev-542f869f1826f092606efd0c4c771f070d1314f5.tar.gz
Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into devel
Conflicts: arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/head.S26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index d14b827..b371fba 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -465,6 +465,20 @@ __armv7_mmu_cache_on:
mcr p15, 0, r0, c7, c5, 4 @ ISB
mov pc, r12
+__fa526_cache_on:
+ mov r12, lr
+ bl __setup_mmu
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+ mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
+ mrc p15, 0, r0, c1, c0, 0 @ read control reg
+ orr r0, r0, #0x1000 @ I-cache enable
+ bl __common_mmu_cache_on
+ mov r0, #0
+ mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
+ mov pc, r12
+
__arm6_mmu_cache_on:
mov r12, lr
bl __setup_mmu
@@ -654,6 +668,12 @@ proc_types:
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
+ .word 0x66015261 @ FA526
+ .word 0xff01fff1
+ b __fa526_cache_on
+ b __armv4_mmu_cache_off
+ b __fa526_cache_flush
+
@ These match on the architecture ID
.word 0x00020000 @ ARMv4T
@@ -793,6 +813,12 @@ __armv4_mpu_cache_flush:
mcr p15, 0, ip, c7, c10, 4 @ drain WB
mov pc, lr
+__fa526_cache_flush:
+ mov r1, #0
+ mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
+ mcr p15, 0, r1, c7, c5, 0 @ flush I cache
+ mcr p15, 0, r1, c7, c10, 4 @ drain WB
+ mov pc, lr
__armv6_mmu_cache_flush:
mov r1, #0
OpenPOWER on IntegriCloud