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author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-09 10:07:33 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-09 10:07:33 -0700 |
commit | c6778ff813d2ca3e3c8733c87dc8b6831a64578b (patch) | |
tree | cc0a79f229fdcd723a7597500dcda06e6a4d9deb /arch/arm/boot | |
parent | 0ff4c01b279a590a2826ade9321ad8c7ca5a1b6c (diff) | |
parent | 3c0e3abd5ee59acbcbd5d8fc624eaf63f6e7b53c (diff) | |
download | op-kernel-dev-c6778ff813d2ca3e3c8733c87dc8b6831a64578b.zip op-kernel-dev-c6778ff813d2ca3e3c8733c87dc8b6831a64578b.tar.gz |
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/meson8b.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 |
3 files changed, 18 insertions, 31 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 45619f6..ebc763e 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -106,6 +106,7 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 120>; }; spi_nor_pins: nor { @@ -148,6 +149,7 @@ reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 120 16>; }; uart_ao_a_pins: uart_ao_a { diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 41fd536..828aa49 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -198,6 +198,7 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 130>; }; }; @@ -215,6 +216,7 @@ reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 130 16>; }; uart_ao_a_pins: uart_ao_a { diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6640ebfa..1aeeacb 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -68,31 +68,12 @@ clock-output-names = "osc32k"; }; - apb0: apb0_clk { - compatible = "fixed-factor-clock"; + iosc: internal-osc-clk { #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk@01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; }; }; @@ -576,9 +557,12 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; #reset-cells = <1>; }; @@ -589,9 +573,9 @@ ir: ir@01f02000 { compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; + clocks = <&r_ccu 4>, <&r_ccu 11>; clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; + resets = <&r_ccu 0>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x40>; status = "disabled"; @@ -601,9 +585,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; interrupt-controller; |