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authorNicolas Chauvet <kwizart@gmail.com>2015-08-08 15:58:12 +0200
committerThierry Reding <treding@nvidia.com>2015-08-21 18:44:28 +0200
commit0d5ccb38d19574fecfa471205317d37221ec59a7 (patch)
treeb928c9fe5a9c6ab180220755d100aaf94a12eea5 /arch/arm/boot/dts
parent82fe42f5d7b01848a6fc2aee150a4050ca56b1e0 (diff)
downloadop-kernel-dev-0d5ccb38d19574fecfa471205317d37221ec59a7.zip
op-kernel-dev-0d5ccb38d19574fecfa471205317d37221ec59a7.tar.gz
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
Current base address is wrong by 0x04 bytes for AHB bus device as shown in dmesg: tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround To correct old DTBs, commit ce7a10b0ff3d ("ARM: 8334/1: amba: tegra-ahb: detect and correct bogus base address") checks for the low bit of the base address and removes theses 0x04 bytes at runtime. This patch fixes the original DTS, so upstream version doesn't need the workaround of the base address. As both addresses are valid, this patch doesn't break compatibility. Tested on tegra20-paz00 (aka ac100). Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi4
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index f58a3d9..4bdf8f9 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -214,9 +214,9 @@
#dma-cells = <1>;
};
- ahb: ahb@6000c004 {
+ ahb: ahb@6000c000 {
compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
- reg = <0x6000c004 0x14c>;
+ reg = <0x6000c000 0x150>;
};
gpio: gpio@6000d000 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f444b67..f6f1461 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -225,9 +225,9 @@
#dma-cells = <1>;
};
- ahb@6000c004 {
+ ahb@6000c000 {
compatible = "nvidia,tegra20-ahb";
- reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
+ reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
};
gpio: gpio@6000d000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 782b11b..559763e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -329,9 +329,9 @@
#dma-cells = <1>;
};
- ahb: ahb@6000c004 {
+ ahb: ahb@6000c000 {
compatible = "nvidia,tegra30-ahb";
- reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
+ reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
};
gpio: gpio@6000d000 {
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