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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2013-07-31 16:24:59 -0700
committerMichal Simek <michal.simek@xilinx.com>2013-08-13 16:37:35 +0200
commit39c41df9c1950fba0ee6a4e7a63be281e89fe437 (patch)
tree793a5765c09ff57451c33a255aa0575be950cf51 /arch/arm/boot/dts/zynq-7000.dtsi
parentd4e4ab86bcba5a72779c43dc1459f71fea3d89c8 (diff)
downloadop-kernel-dev-39c41df9c1950fba0ee6a4e7a63be281e89fe437.zip
op-kernel-dev-39c41df9c1950fba0ee6a4e7a63be281e89fe437.tar.gz
arm: zynq: dt: Set correct L2 ram latencies
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6f54a64..e32b92b 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -41,8 +41,8 @@
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
- arm,data-latency = <2 3 2>;
- arm,tag-latency = <2 3 2>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
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