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authorTony Prisk <linux@prisktech.co.nz>2013-05-17 21:30:05 +1200
committerTony Prisk <linux@prisktech.co.nz>2013-06-04 07:31:22 +1200
commite36572b64df358f0bc3a508e8761c81d7f3b8215 (patch)
treeaf553a9714e8e71e26f1d80431e3e5548234814e /arch/arm/boot/dts/wm8850.dtsi
parent9e7b6d3eda8551912b0cf9507ca5f489a476d522 (diff)
downloadop-kernel-dev-e36572b64df358f0bc3a508e8761c81d7f3b8215.zip
op-kernel-dev-e36572b64df358f0bc3a508e8761c81d7f3b8215.tar.gz
dts: vt8500: Correct reference clock on WM8850 SoCs
WM8850 SoCs use a 24Mhz reference clock for the PLLs but the SoC file currently parents all PLLs to the 25Mhz reference clock. This patch corrects the PLL parent clock references. Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Diffstat (limited to 'arch/arm/boot/dts/wm8850.dtsi')
-rw-r--r--arch/arm/boot/dts/wm8850.dtsi14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index 1f49f54..d98386d 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -84,49 +84,49 @@
plla: plla {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x200>;
};
pllb: pllb {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x204>;
};
pllc: pllc {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x208>;
};
plld: plld {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x20c>;
};
plle: plle {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x210>;
};
pllf: pllf {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x214>;
};
pllg: pllg {
#clock-cells = <0>;
compatible = "wm,wm8850-pll-clock";
- clocks = <&ref25>;
+ clocks = <&ref24>;
reg = <0x218>;
};
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