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authorStephen Warren <swarren@nvidia.com>2013-01-23 09:43:49 -0700
committerStephen Warren <swarren@nvidia.com>2013-01-28 11:24:09 -0700
commitabf80c276dca1bf40b342b4ebf7815be0f6ba564 (patch)
tree4b90282b64e4f0b74200c120c96206c052dd6dfa /arch/arm/boot/dts/tegra30.dtsi
parentbf5fcc76d31418950b214542440d5de6e48c7998 (diff)
downloadop-kernel-dev-abf80c276dca1bf40b342b4ebf7815be0f6ba564.zip
op-kernel-dev-abf80c276dca1bf40b342b4ebf7815be0f6ba564.tar.gz
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ff4a0ca..313fa71 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -234,6 +234,7 @@
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
+ clock-frequency = <408000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
status = "disabled";
@@ -243,6 +244,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>;
@@ -253,6 +255,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
@@ -263,6 +266,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 90 0x04>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
@@ -273,6 +277,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 91 0x04>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
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