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| author | Chen-Yu Tsai <wens@csie.org> | 2015-01-28 03:54:08 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-04-27 08:20:17 +0200 |
| commit | bc8ffc2de87855f91b376dca4597ca0b9254cabc (patch) | |
| tree | acf90cceb71bc0c57e4abea9c8b0fde552c04703 /arch/arm/boot/dts/sun9i-a80.dtsi | |
| parent | d67b984be92927c1bbab3e391616e51937e26438 (diff) | |
| download | op-kernel-dev-bc8ffc2de87855f91b376dca4597ca0b9254cabc.zip op-kernel-dev-bc8ffc2de87855f91b376dca4597ca0b9254cabc.tar.gz | |
ARM: dts: sun9i: Add usb clock nodes to a80 dtsi
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun9i-a80.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f0f6fb9..0ffecf6 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -137,6 +137,28 @@ clock-output-names = "osc32k"; }; + usb_mod_clk: clk@00a08000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-mod-clk"; + reg = <0x00a08000 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb0_ahb", "usb_ohci0", + "usb1_ahb", "usb_ohci1", + "usb2_ahb", "usb_ohci2"; + }; + + usb_phy_clk: clk@00a08004 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-phy-clk"; + reg = <0x00a08004 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb_phy0", "usb_hsic1_480M", + "usb_phy1", "usb_hsic2_480M", + "usb_phy2", "usb_hsic_12M"; + }; + pll4: clk@0600000c { #clock-cells = <0>; compatible = "allwinner,sun9i-a80-pll4-clk"; |
