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authorMilo Kim <woogyom.kim@gmail.com>2016-10-28 15:54:09 +0900
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-11-22 15:34:01 +0100
commiteeeb2d64e8d656f879d7e1d54da3931b92962d3e (patch)
tree986fe801154a5088102b51cd32b79ec2fbb6288a /arch/arm/boot/dts/sun8i-h3.dtsi
parent10efbf5f16336b7540ad6a16aa1cb0b26bab033b (diff)
downloadop-kernel-dev-eeeb2d64e8d656f879d7e1d54da3931b92962d3e.zip
op-kernel-dev-eeeb2d64e8d656f879d7e1d54da3931b92962d3e.tar.gz
ARM: dts: sun8i: Add SPI pinctrl node in H3
H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are configured through the pinctrl subsystem. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-h3.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75a8654..8a59d8d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -381,6 +381,20 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ spi0_pins: spi0 {
+ allwinner,pins = "PC0", "PC1", "PC2", "PC3";
+ allwinner,function = "spi0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi1_pins: spi1 {
+ allwinner,pins = "PA15", "PA16", "PA14", "PA13";
+ allwinner,function = "spi1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PA4", "PA5";
allwinner,function = "uart0";
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