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authorDinh Nguyen <dinguyen@altera.com>2013-09-25 15:38:20 -0500
committerDinh Nguyen <dinguyen@altera.com>2013-10-09 16:58:31 -0500
commit163a036468c2eb8f30658dff6c0de6c959f79b0d (patch)
treecd66f1beb44868b9f29fc9355ac2cd67c38f754d /arch/arm/boot/dts/socfpga_arria5.dtsi
parent01ed80b07dadc8747468bd738c8cbfcaf0169866 (diff)
downloadop-kernel-dev-163a036468c2eb8f30658dff6c0de6c959f79b0d.zip
op-kernel-dev-163a036468c2eb8f30658dff6c0de6c959f79b0d.tar.gz
dts: socfpga: Add support for Altera's SOCFPGA Arria V board
Add support for a new SOCFPGA board that has an Arria V FPGA along with dual ARM Cortex-A9 cores. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria5.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi58
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
new file mode 100644
index 0000000..a85b404
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+
+ serial0@ffc02000 {
+ clock-frequency = <100000000>;
+ };
+
+ serial1@ffc03000 {
+ clock-frequency = <100000000>;
+ };
+
+ sysmgr@ffd08000 {
+ cpu1-start-addr = <0xffd080c4>;
+ };
+
+ timer0@ffc08000 {
+ clock-frequency = <100000000>;
+ };
+
+ timer1@ffc09000 {
+ clock-frequency = <100000000>;
+ };
+
+ timer2@ffd00000 {
+ clock-frequency = <25000000>;
+ };
+
+ timer3@ffd01000 {
+ clock-frequency = <25000000>;
+ };
+ };
+};
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