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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-23 13:59:25 +0200 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2017-09-19 11:19:42 +0200 |
commit | 362b334b17943d84d2878d2733f0ce695d45a2b6 (patch) | |
tree | 4c66413c75bf8073061175a9bec046b12338a470 /arch/arm/boot/dts/r8a7791-porter.dts | |
parent | a7b8f48d2fa14330a1886f7fd640187c8b4470c5 (diff) | |
download | op-kernel-dev-362b334b17943d84d2878d2733f0ce695d45a2b6.zip op-kernel-dev-362b334b17943d84d2878d2733f0ce695d45a2b6.tar.gz |
ARM: dts: r8a7791: Convert to new CPG/MSSR bindings
Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791-porter.dts')
-rw-r--r-- | arch/arm/boot/dts/r8a7791-porter.dts | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 95da5cb..eb37495 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -419,9 +419,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x3_clk>, <&x16_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; |