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| author | Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> | 2014-10-14 16:01:42 +0900 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-10-30 09:56:28 +0900 |
| commit | 4ba8f2468ce346642b4ace3cdf4bdd8d29175011 (patch) | |
| tree | e4b3a3ed358dc2d70574980ade4b70cb094fdf57 /arch/arm/boot/dts/r8a7790.dtsi | |
| parent | e4d2fd9eb43d12e9b6a7ab842bf6986b4dd75a1d (diff) | |
| download | op-kernel-dev-4ba8f2468ce346642b4ace3cdf4bdd8d29175011.zip op-kernel-dev-4ba8f2468ce346642b4ace3cdf4bdd8d29175011.tar.gz | |
ARM: shmobile: r8a7790: Add MMP clock to device tree
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 602a46a..050e608 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -977,18 +977,24 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; + clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, + <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_3DG - R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 - R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 - R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S + R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 + R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 + R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC + R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 + R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 + R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 + R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = - "jpu", "tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0", + "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", + "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", + "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { |
