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| author | Biju Das <biju.das@bp.renesas.com> | 2017-08-08 11:56:32 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-08-17 10:32:49 +0200 |
| commit | 60dce695b097a52e6ea5874aa80301f2e4ac627a (patch) | |
| tree | ac245a8e5ab0be2dcf14d8a75adc9410ea321964 /arch/arm/boot/dts/r8a7743.dtsi | |
| parent | 02a5ab18d366223893d634b0992f6434300bee32 (diff) | |
| download | op-kernel-dev-60dce695b097a52e6ea5874aa80301f2e4ac627a.zip op-kernel-dev-60dce695b097a52e6ea5874aa80301f2e4ac627a.tar.gz | |
ARM: dts: r8a7743: Add APMU node and second CPU core
Add DT nodes for the Advanced Power Management Unit (APMU) and the
second CPU core. Use the enable-method to point out that the APMU
should be used for SMP support.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7743.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index ce80a26..ec9db0f 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -30,6 +30,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -41,6 +42,15 @@ next-level-cache = <&L2_CA15>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + L2_CA15: cache-controller-0 { compatible = "cache"; cache-unified; @@ -57,6 +67,12 @@ #size-cells = <2>; ranges; + apmu@e6152000 { + compatible = "renesas,r8a7743-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |
