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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2016-02-23 14:14:26 +0000
committerAndy Gross <andy.gross@linaro.org>2016-02-26 13:15:48 -0600
commit64b22b2594b1832ad21fce4969818e774d329551 (patch)
treec054f83a6a06dc2eae6132a26850e0a0d8a64c36 /arch/arm/boot/dts/qcom-apq8064-pins.dtsi
parent9d0801a09cf8bea480d81d1292be83d0bdc14283 (diff)
downloadop-kernel-dev-64b22b2594b1832ad21fce4969818e774d329551.zip
op-kernel-dev-64b22b2594b1832ad21fce4969818e774d329551.tar.gz
ARM: dts: apq8064: add i2c sleep pinctrl states.
This patch adds missing i2c pinctrl sleep states. Also add 16mA drive strength to the pins so that we can detect wide range of i2c devices on the other side of level shifters. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-apq8064-pins.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-pins.dtsi36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index c711aca..ce15c67 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -19,6 +19,24 @@
pins = "gpio20", "gpio21";
function = "gsbi1";
};
+
+ pinconf {
+ pins = "gpio20", "gpio21";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_sleep: i2c1_pins_sleep {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "gpio";
+ };
+ pinconf {
+ pins = "gpio20", "gpio21";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
};
i2c3_pins: i2c3 {
@@ -26,6 +44,24 @@
pins = "gpio8", "gpio9";
function = "gsbi3";
};
+
+ pinconf {
+ pins = "gpio8", "gpio9";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_sleep: i2c3_pins_sleep {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "gpio";
+ };
+ pinconf {
+ pins = "gpio8", "gpio9";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
};
gsbi6_uart_2pins: gsbi6_uart_2pins {
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