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authorRoland Stigge <stigge@antcom.de>2012-06-14 16:16:18 +0200
committerRoland Stigge <stigge@antcom.de>2012-06-14 16:16:18 +0200
commitc70426f1534a7d8e52e478ce67fd4634cc588741 (patch)
tree8ca73976d4ea43c4ecbcc0681b324d0215e1ca3f /arch/arm/boot/dts/phy3250.dts
parent2c7fa28622d8c00ca41f0362d11c52d9f404f543 (diff)
downloadop-kernel-dev-c70426f1534a7d8e52e478ce67fd4634cc588741.zip
op-kernel-dev-c70426f1534a7d8e52e478ce67fd4634cc588741.tar.gz
ARM: LPC32xx: DT conversion of Standard UARTs
This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/phy3250.dts')
-rw-r--r--arch/arm/boot/dts/phy3250.dts8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index d543237..57d4961 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -94,6 +94,14 @@
};
apb {
+ uart5: serial@40090000 {
+ status = "okay";
+ };
+
+ uart3: serial@40080000 {
+ status = "okay";
+ };
+
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
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