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authorShawn Guo <shawn.guo@linaro.org>2013-02-20 10:32:52 +0800
committerShawn Guo <shawn.guo@linaro.org>2013-04-09 22:52:50 +0800
commite16415313c9b00b1adc313e85c2c8a81febe0b98 (patch)
treeb1e804b1bb647f3984036d9f9befbe53023bc519 /arch/arm/boot/dts/imx6q-arm2.dts
parent36dffd8f49bc1364998db81bee739ea4574d88f7 (diff)
downloadop-kernel-dev-e16415313c9b00b1adc313e85c2c8a81febe0b98.zip
op-kernel-dev-e16415313c9b00b1adc313e85c2c8a81febe0b98.tar.gz
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-arm2.dts')
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 8f6ec9a..4e54fde 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -57,7 +57,7 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
- 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+ MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
>;
};
};
@@ -65,8 +65,8 @@
arm2 {
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
fsl,pins = <
- 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
- 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+ MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+ MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
>;
};
};
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