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authorKrzysztof Kozlowski <k.kozlowski@samsung.com>2015-04-03 11:28:01 +0200
committerKukjin Kim <kgene@kernel.org>2015-06-03 09:46:52 +0900
commit8d9321fbe2be1b403ac861930ed87d4b36d9febc (patch)
treef64160b7d93862ef55e7e5579d79d41cd62e1408 /arch/arm/boot/dts/exynos5420.dtsi
parenta1c0013c71e191f0fe256db42c92a6b26909224a (diff)
downloadop-kernel-dev-8d9321fbe2be1b403ac861930ed87d4b36d9febc.zip
op-kernel-dev-8d9321fbe2be1b403ac861930ed87d4b36d9febc.tar.gz
ARM: dts: Use last parent for clocks during power domain on/off
Replace fixed parent with last parent (obtained with clk_get_parent()) of clocks for devices in mfc and disp power domains. This should improve behavior if such clocks were reparented by the drivers and new parents are different than those specified in DTS. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi13
1 files changed, 4 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8ab4421..7bf7a61 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -264,9 +264,8 @@
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044060 0x20>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
- <&clock CLK_MOUT_USER_ACLK333>;
- clock-names = "oscclk", "pclk0", "clk0";
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
+ clock-names = "oscclk", "clk0";
#power-domain-cells = <0>;
};
@@ -280,16 +279,12 @@
compatible = "samsung,exynos4210-pd";
reg = <0x100440C0 0x20>;
#power-domain-cells = <0>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
+ clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK200_DISP1>,
- <&clock CLK_MOUT_SW_ACLK300>,
<&clock CLK_MOUT_USER_ACLK300_DISP1>,
- <&clock CLK_MOUT_SW_ACLK400>,
<&clock CLK_MOUT_USER_ACLK400_DISP1>,
<&clock CLK_FIMD1>, <&clock CLK_MIXER>;
- clock-names = "oscclk", "pclk0", "clk0",
- "pclk1", "clk1", "pclk2", "clk2",
- "asb0", "asb1";
+ clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
};
pinctrl_0: pinctrl@13400000 {
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