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author | Ray Jui <rjui@broadcom.com> | 2015-09-21 15:12:44 -0700 |
---|---|---|
committer | Florian Fainelli <f.fainelli@gmail.com> | 2015-09-22 17:50:35 -0700 |
commit | ef5b812a4e8d088836e67ade113562ca5ad4579e (patch) | |
tree | cc5b9cbd52d5a28cd7355a284b069db6241f596c /arch/arm/boot/dts/bcm-cygnus.dtsi | |
parent | 5b159b62eb2a6799d9dbe998d7635b346ca6fdf8 (diff) | |
download | op-kernel-dev-ef5b812a4e8d088836e67ade113562ca5ad4579e.zip op-kernel-dev-ef5b812a4e8d088836e67ade113562ca5ad4579e.tar.gz |
ARM: dts: Put Cygnus core components under core bus
Put all Cygnus core components into "core" node of type "simple-bus" in
bcm-cygnus.dtsi
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm-cygnus.dtsi')
-rw-r--r-- | arch/arm/boot/dts/bcm-cygnus.dtsi | 54 |
1 files changed, 30 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 30903ba..97fd305 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -58,6 +58,36 @@ /include/ "bcm-cygnus-clock.dtsi" + core { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + pinctrl: pinctrl@0x0301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x30>, @@ -227,28 +257,4 @@ brcm,nand-has-wp; }; - - gic: interrupt-controller@19021000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x19021000 0x1000>, - <0x19020100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x19022000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - timer@19020200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x19020200 0x100>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&periph_clk>; - }; - }; |