diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2014-09-04 16:45:56 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2014-11-20 23:08:42 -0600 |
| commit | 475dc86d08de4af61b6e8524bbcdbf8d675cb4fa (patch) | |
| tree | 499b98442fdd1c59461e1d10f057f2836fa25ba8 /arch/arm/boot/dts/Makefile | |
| parent | c1ad85d77224b91448761a3f0ab0d14459c7bb44 (diff) | |
| download | op-kernel-dev-475dc86d08de4af61b6e8524bbcdbf8d675cb4fa.zip op-kernel-dev-475dc86d08de4af61b6e8524bbcdbf8d675cb4fa.tar.gz | |
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10
SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there
are enough differences to warrant a new base dtsi.
The differences are:
* 3 EMAC controllers
* 5 I2C controllers
* 3 SPI controllers
* 1.5 GHZ dual A9s
* Support for DDR4
Besides the usual memory map and IRQ changes, the clock framework will be
different, so this patch just adds the fixed-clocks.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/Makefile')
| -rw-r--r-- | arch/arm/boot/dts/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 38c89ca..b1905a7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -397,6 +397,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ r8a7779-marzen.dtb \ r8a7794-alt.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ |
