diff options
| author | Olof Johansson <olof@lixom.net> | 2015-07-28 18:25:39 +0200 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-07-28 18:25:39 +0200 |
| commit | 46a51abbda4ed0d09cc1ea6937f31e322a88c517 (patch) | |
| tree | 981e830845a10b58279bf68db472f072c1ae2c6d /arch/arm/boot/dts/Makefile | |
| parent | 55e3cfc5f9a7303d78026bcf4bdfb1788b669ea0 (diff) | |
| parent | 2e4c7588f6c1d24ae991a85140e05139e953c9b5 (diff) | |
| download | op-kernel-dev-46a51abbda4ed0d09cc1ea6937f31e322a88c517.zip op-kernel-dev-46a51abbda4ed0d09cc1ea6937f31e322a88c517.tar.gz | |
Merge tag 'socfpga_dts_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.3
- Update clocking for DTS nodes
- Add DTS board file for Terasic DE0 Atlas board
- Use stdout-patch for chosen node
- Enable prefetch-data and prefetch-instr
* tag 'socfpga_dts_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
ARM: socfpga: dts: add missing clock gates to socfpga.dtsi
ARM: socfpga: dts: Fix gpio dts entry for the correct clock
ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
ARM: dts: socfpga: Add support of Terasic DE0 Atlas board
ARM: dts: socfpga: use stdout-path for chosen node
ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/Makefile')
| -rw-r--r-- | arch/arm/boot/dts/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9dd04e2..4afd369 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -536,6 +536,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_vt.dtb |
